Incoming Analog Signal Research Articles

Design and implementation of a new high-accuracy interpolation encoder IC for magneto-resistive sensors

A new algorithm named the eight-section (ES) method for carrying out the interpolation for a magneto-resistive (MR) encoder is successfully developed and fabricated in a digital chip. It is known that a conventional magneto-resistive (MR) encoder employs the interpolation method, which converts incoming front-end analog signals in harmonics in sinusoids/co-sinusoids to moving displacement via calculating arc-tangents. This conventional interpolation requires divisions to be carried out for the displacement, which often leads to large noises while conducting digital computation, eventually undermining significantly the accuracy of the MR sensor. The proposed interpolation of eight-section (ES) is designed specially without divisions in the digital computation, leading to higher precision than the conventional interpolation conducting the computation of arc-tangents. The digital computation chip designed by this study consists of a cycle counter, two decimators for incoming analog signals of the MR sensor, a correcting circuit, and the proposal ES interpolation unit. The designed chip is successfully fabricated by TSMC 0.18-μm CMOS process, the area of which is 1643 × 1676 μm. The chip is than calibrated by a reference interferometer by experiments for further improving the measurement accuracy. The precision finally results in measuring displacement reaches as accurate as within 1.065 μm, which is much favorable to the existing performance around 2 μm by the conventional interpolation.

Analog Network Coding Mappings in Gaussian Multiple-Access Relay Channels

We consider the multiple-access relay channel with two source nodes, one relay node and one destination node. For practical simplicity, we consider orthogonal transmission of the source messages and half-duplex relaying. We also assume that the relay is memoryless and is implemented based on a two-to-one deterministic mapping. Our focus is on proposing and investigating such mappings. Essentially, the proposed relaying functions combine the two incoming analog signals and forward them to the destination, thus we term them as analog network coding mappings. Both linear and non-linear relaying are investigated for the multiple-access relay channel and the special case of the multiple-access two-hop channel. In particular, we suggest to use mappings based on the Archimedean spiral for analog non-linear combining. In addition, we propose to couple spiral mappings with sawtooth-like mappings to exploit the potential side information provided by the direct links of the multiple-access relay channel. In the case of symmetric topology, our proposed scheme can be seen as an extension to the amplify-and-forward scheme, where the asymmetric input/output dimensionality in the relay node is handled before amplifying. We investigate the resulting achievable rate regions and sum rates, and demonstrate significant gains over conventional relaying schemes.

WIDEBAND ANALOG VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORKS

This paper presents an analog VLSL circuit for implementation of Artificial Neural Networks (ANNs ). The building blocks of the proposed circuit include Differential voltage current controlled source (DVCCS), Super MOSFET and Differential voltage controlled voltage source (DVCVS) which are used to multiply incoming analog signals with variable weights, and current in / current out sigmoid function circuit. The proposed circuit can be easily implemented in a 0.34 μ m CMOS VLSI process. Simulations are presented to confirm the validity of the proposed circuit.

Timing jitter in digital filtering of analog signals

Effects of timing jitter in digital filtering of analog signals are analyzed. Jitter may be introduced into the system when the incoming analog signal is being sampled and when the samples of the output of the digital filter are being read out for reconstruction back into an analog signal. These two jitters are called readin and readout jitters, respectively. General expressions are derived for the spectrum of the analog output in the presence of jitter and for the mean-square error introduced by the jitter. Four specific cases are then considered. They are readin jitter only, readout jitter only, independent jitter, and locked jitter. In each case, the general expression for the spectrum of the analog output is reduced to a more explicit form, and a simple upper bound on the mean-square error is derived. An example is included to illustrate the effect of high-frequency jitter and the effect of jitter due to 60-cycle pickup.

First-Order Discrete Phase-Locked Loop with Applications to Demodulation of Angle-Modulated Carrier

In this paper, a first-order discrete phase-locked loop that tracks the phase of an incoming analog signal at discrete instants of time occurring once per cycle of the carrier is developed. The functional loop components and the operation of the loop are described in detail. The loop model is developed for both the deterministic and noisy case by a nonlinear coupled difference equation with perturbed (or deviating) arguments. The tracking performance for the inputs of the phase step, the phase ramp, and the sinusoidally modulated carrier is determined and the locking conditions for these input transients are derived. Conceptual designs using this first-order digital loop have been given for the demodulation of phase- and frequency-modulated signals.