Including Testing Pads Research Articles

A 27–35 GHz wideband PIN-diode limiter low noise amplifier MMIC with sub-2.4 dB noise figure

In this paper, a thorough co-design procedure for the integrated PIN-diode limiter and low noise amplifier (LNA) is presented. A 27 GHz–35 GHz wideband integrated limiter low noise amplifier (limiter-LNA) is fabricated with the combined PIN/0.15-μm-pHEMT technology for millimeter-wave radar applications. The PIN-diode limiter and the LNA are co-designed to improve the small signal performance. To improve the noise performance and the input-matching of the limiter-LNA, a novel limiter design method with the modified lossy TL model is presented. The measurement results illustrate that the small-signal gain is 20 ± 0.7 dB, the noise figure (NF) is 1.9 dB–2.4 dB, the output power at 1 dB compression point (OP1dB) is larger than 12.1 dBm and the dc power consumption is only 96-mW. The limiter-LNA is capable of handling 38 dBm continuous wave (CW) input-power without failure. The chip area including testing pads is 2.3 mm × 1.0 mm.

A Wideband High-Efficiency GaN MMIC Power Amplifier for Sub-6-GHz Applications.

The monolithic microwave integrated circuit (MMIC) power amplifiers serve an essential and critical role in RF transmit/receive (T/R) modules of phased array radar systems, mobile communication systems and satellite systems. Over recent years, there has been an increasing requirement to develop wideband high-efficiency MMIC high power amplifiers (HPAs) to accommodate wideband operation and reduce power consumption. This paper presents a wideband high efficiency MMIC HPA for Sub-6-GHz applications using a 0.25-μm gate-length D-mode GaN/SiC high electron mobility transistor (HEMT) process. The amplifier consists of two stages with two HEMT cells for the driver stage and eight HEMT cells for the power stage. To obtain a flat gain while maintaining the wideband characteristic, a gain equalization technique is employed in the inter-stage matching circuit. Meanwhile, a low-loss output matching network is utilized to ensure high efficiency. The fabricated HPA occupies a compact chip area of 14.35 mm2 including testing pads. Over the frequency range of 2–6 GHz, measured results of this HPA show a saturated continuous wave (CW) output power of 44.4–45.2 dBm, a power added efficiency (PAE) of 35.8–51.3%, a small signal gain of 24–25.5 dB, and maximum input and output return losses of 14.5 and 10 dB, respectively.

A compact Ka‐band limiter‐low noise amplifier MMIC with high power capability

AbstractThis paper presents a 30–36 GHz limiter low‐noise amplifier (limiter‐LNA) MMIC for high power and high mobility millimeter‐wave radar systems. The PIN‐diode limiter network and the LNA are codesigned to realize high input‐power handling capability, good small‐signal performance, and small chip area. A two‐state matching capacitor is presented to improve both the input‐power handling capability at the high input‐power level and the input return loss at the small‐signal level. The proposed circuit is fabricated with a combined PIN/0.15‐µm‐GaAs‐pHEMT process. The limiter‐LNA is capable of handling 39 dBm continuous wave (CW) input‐power without failure with only two limiter stages. The measured noise figure is 1.8–2.5 dB, the small‐signal gain is 18.5 ± 0.5 dB, the output power at 1 dB compression point is larger than 11 dBm, and the dc power consumption is 72 mW. The chip area, including testing pads, is only 2.1 mm × 1.0 mm. This limiter‐LNA MMIC is believed to have the highest input‐power handling capability and smallest chip area among limiter‐LNA MMICs at this frequency range reported up to date.

A low power broadband LC-VCO using high quality-factor multi-path stacked inductors in 14-nm FinFET

A broadband cross-coupled inductance-capacitance voltage-controlled oscillator (LC-VCO) is designed and implemented in 14-nm FinFET. To improve the tuning range and reduce phase noise of the VCO, novel multi-path stacked inductors are employed. A binary-weighted FinFET varactor array is utilized for band selection and frequency tuning at the same time without degrading the quality factor. The sizes of the FinFET devices are optimized to decrease the power consumption of the VCO. The chip size of the LC-VCO is 618 μm × 630 μm including testing pads. Measurement results demonstrate the frequency tuning range is 30.3%, phase noise is −112.5 dBc/Hz @ 1 MHz offset from 10.086 GHz carrier frequency and the power consumption is only 1.5 mW under 0.75 V supply voltage.

Analysis and Design of a Broadband Receiver Front End for 0.1-to-40-GHz Application

In this paper, a broadband receiver front end for 0.1 to 40 GHz application, fabricated using 0.15-μm GaAs E-mode pHEMT process, is reported. The receiver front end consists of a broadband low-noise amplifier (LNA) and a broadband mixer. To achieve low noise and significant bandwidth extension, a three-stage LNA, cascading one stage cascode amplifier with feedback and bandwidth extension techniques, to two stage cascode Darlington amplifiers with feedback, is proposed. The bandwidth extension principles of LNA are analyzed theoretically and verified experimentally. Measurement results show that the proposed LNA exhibits an average gain of 23.7 dB with ± 1.5-dB variation, a typical noise figure of 3.8 dB, maximum OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> of 8.7 dBm in the frequency range from 0.1 to 40 GHz. A symmetric distributed drain mixer (SDDM) is proposed to provide broad bandwidth while ensuring an IP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> of up to 5.8 dBm. The design procedure of SDDM is presented in detail. Experimental results indicate that the SDDM features a less than 7-dB conversion loss, an IP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> of up to 5.8 dBm with zero dc dissipation and better than 15-dB isolation of LO-to-RF and IF-to-RF ports from 0.1 to 40 GHz. Finally, the LNA and SDDM are integrated as a 0.1 to 40-GHz receiver front end. Measurements illustrate that the receiver front end shows good matching with better than 10-dB return loss at RF and LO ports, and larger than 15-dB conversion gain in 0.1 to 40-GHz frequency range. The receiver occupies only 1.89-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip area including test pads. To the best of the authors' knowledge, the designed receiver front end has the widest bandwidth among reported receivers fabricated by using GaAs process.

High gain 0.18 μm-GaAs MMIC cascode-distributed low-noise amplifier for UWB application

This paper describes a design of 3 GHz–12 GHz MMIC distributed Low Noise Amplifiers (LNAs) for Ultra Wideband communications systems. The proposed circuit is a common source and cascode topology using a standard 0.18 μm ED02AH process from OMMIC foundry. The ultra-wideband LNA achieves a power gain of 16.9 ± 1.7 dB and an average noise figure of 2.9 ± 0.58 dB. The input and output reflection coefficients are less than −10 dB, the reverse gain S12 is less than −37dB and a high linearity IIP3 of [4–6.2] dBm. The chip area including testing pads is only about 1.3 × 1.3 mm2.

A Compact Broadband Monolithic Sub-Harmonic Mixer Using Multi-Line Coupler

A compact broadband monolithic sub-harmonic mixer is presented in a 70 nm GaAs Technology for millimeter wave wireless communication application. The proposed mixer adopts a novel multi-line coupler structure; where the two-sided coupling energy of radio frequency (RF) and local oscillation (LO) signals are both collected and efficiently feed to anti-parallel diode pair (APDP) topology; resulting in broadband performance and compact chip size. As a comparison in the same circuit configuration; the five-line coupler can expand the bandwidth of the existing three-line coupler by 85% and reduce the area by 39.5% when the central frequency is 127 GHz. The measured conversion gain is −16.2 dB to −19.7 dB in a wide operation frequency band of 110–170 GHz. The whole chip size is 0.47 × 0.66 mm2 including test pads. The proposed mixer exhibits good figure-of-merits for D-band down-converter applications

A 20.5 dBm Outphasing Class-F PA with Chireix Architecture at 3.5 GHz for RF Transmitter Front-end

An outphasing class-F power amplifier (PA) with Chireix architecture is presented in Global Foundry (GF) 0.13µm Complementary Metal Oxide Semiconductor (CMOS) technology. The proposed circuit is composed of two branch class-F PA and Chireix power combiner with a floating load. The designed outphasing amplifier can provide 20.5 dBm output power from 1.8 V power supply at 3.5 GHz with 52.9 % power added efficiency (PAE). Wideband Code Division Multiple Access (W-CDMA) signal is implemented as input signal to simulate ACPR and the adjacent channel leakage ratios (ACLRs) at ±5 MHz are -20.5 dBc/-20.7dBc. After DPD (Digital Pre-Distortion) ACLRs can achieve -44.5 dBc/-44.7dBc at ±5 MHz. Furthermore, the chip area including testing pads is 1.98*1.62 mm2.

A 3.5-GHz Class-F Power Amplifier with Current-Reused Topology in 0.13-μm CMOS for 5G Application

In this paper, a 3.5-GHz class-F Power Amplifier with current-reused topology in 0.13-[Formula: see text]m CMOS for 5G application is presented. This proposed circuit has a two-stage structure by a current-reused topology driving to improve gain and the stability of PA. An output matching network is constructed by an open-circuited third harmonic resonator that can integrate the current and voltage waveform in the time domain adopted to improve the output power and reduce power consumption. The simulation results show that the proposed PA provides a 13[Formula: see text]dBm output power with a PAE of 50.5% and a small signal gain of 32.5[Formula: see text]dB that is higher than reported for a two-stage design in CMOS at the 3.5-GHz frequency, while the minimum output return loss ([Formula: see text]) is [Formula: see text]14.4[Formula: see text]dB with a minimum value of [Formula: see text]24.67[Formula: see text]dB. Many experiments are carried out to prove that the proposed PA has higher gain and higher efficiency compared to the traditional class-F power amplifier and is suitable for 5G short-range applications. Finally, the layout occupies a compact chip area of [Formula: see text][Formula: see text]mm2, including testing pads.

A 77-GHz Mixed-Mode FMCW Signal Generator Based on Bang-Bang Phase Detector

A 77-GHz frequency-modulated continuous-wave (FMCW) signal generator is presented for automobile millimeter-wave (mm-wave) radar applications. The reconfigurable chirp is generated by a mixed-mode synthesizer operating at 38.5 GHz, in which the frequency doubling scheme is used to improve the chirp bandwidth and simplify the design. The bang-bang phase detector (BBPD) is employed for phase detection in the synthesizer, avoiding complicated linear time-to-digital converter (TDC) as well as reducing design complexity and power consumption. A 1-bit third-order single-loop $\Delta \Sigma$ modulator (SLDSM3), combining with the hybrid finite-impulse-response (FIR) filtering technique, significantly suppresses the BBPD induced quantization noise. A type-III slope estimator with a switchable polarity is embedded in the digital loop filter (DLF) to improve the linearity around the chirp turning-around points (TAPs). Two infinite-impulse-response (IIR) filtering stages smoothen the generated chirp waveform by reducing the instant variation of the DLF’s output. Implemented in 65-nm CMOS, the proposed FMCW signal generator consumes 43.1-mW power and occupies 2-mm2 die area, including testing pads. The measured phase noise from the 38.5-GHz carrier is −87.7 dBc/Hz at 1-MHz offset. The measured root-mean-square (rms) frequency errors of the generated triangle chirps over the 1-ms period are 189 and 336 kHz, with 0.914- and 1.827-GHz chirp bandwidth, respectively.

High‐gain mixer using cascode current bleeding and gm‐boosting techniques

ABSTRACTThis paper presents a high‐gain down‐conversion mixer using a cascode current bleeding technique and a transconductance (gm)‐boosting technique. Unlike the conventional folded‐type mixer, an nMOS input transconductance transistor is allocated under pMOS switching transistors and load resistors in the proposed mixer. This topology allows the folded mixer to reuse the total current at the input transconductance transistor for low power consumption and to adopt the current bleeding technique for high gain. In addition, the gm‐boosting technique increases effective transconductance by adding a positive‐feedback inductor. Measured results show a maximum voltage conversion gain of 23.8 dB, an input third‐order intercept point (IIP3) of −10.5 dBm at the maximum gain, a minimum noise figure of 4.3 dB, and a 3‐dB bandwidth from 7.2 to 8.4 GHz with a consumption of 3.9 mW from a 1.2 V supply. The chip size, including test pads, is 0.9 × 0.95 mm2 using 0.13 μm RF CMOS technology. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:1–6, 2017

A Low-Power CMOS Class-E Chireix RF Outphasing Power Amplifier for WLAN Applications

This paper describes the design and implementation of a low-power CMOS class-E Chireix RF outphasing power amplifier (PA) for WLAN applications. The proposed circuit is based on cascode class-E topology with two-stage structure and Chireix power combiner with a floating load. This class-E topology adopts self-biased technique and current-reused technique that avoids using thick-oxide transistors and can enhance the driving ability and power gain. Additionally, the Chireix combiner can reduce the loss of power and improve the efficiency by avoiding the use of isolation resistance. With a 2.5 V power supply, the realized prototype achieved 21.4 dBm of maximum output power and 29.9 % of average power-added efficiency (PAE) at 2.4 GHz. When operated for minimum input levels at 2.5 V, it reached 38.8 dB power gain. For a WLAN OFDM signal with 20 MHz, the error vector magnitude of 3 % is achieved with peak drain efficiency of 62 %. Moreover, the outphasing power amplifier is fully integrated with TSMC 0.18-µm CMOS technology and the chip area including testing pads is 1.07 × 1.17 mm2.

9.5 mW fully integrated K ‐band on–off keying receiver with −47.6 dBm sensitivity and 600 Mbit/s data rate in 90 nm CMOS

A K-band on–off keying (OOK) receiver implemented in tsmcTM 90 nm CMOS process is proposed. The proposed OOK receiver consists of a two-stage wideband low-noise amplifier, a single-to-differential envelop detector with RC lowpass filter and a 62.6 dB three-stage variable gain amplifier and DC offset compensation circuit. The OOK receiver achieved a sensitivity of −47.6 dBm at 600 Mbit/s data rate under a pseudo-random binary sequence 29–1 pattern. The receiver consumes a low power of 9.5 mW, which minimum average power is only 15.86 nW at the input power of −47.6 dBm. The chip area including test pads is 1 × 0.81 mm2.

A Low Power High Gain CMOS LNA with Multiple-Feedback Network for Low Voltage UWB Receiver

In this paper, a high gain low voltage low power Complementary Metal Oxide Semiconductor (CMOS) Low-noise Amplifier (LNA) using Chartered 0.18[Formula: see text][Formula: see text]m CMOS process for Ultra-wideband (UWB) receiver applications is presented. A novel multiple-feedback network constructed by the shunt feedback resistor with a transformer is adopted to realize desirable bandwidth extension and less chip area occupation in the common-source stage. All the cascaded transistors are configured by current-reuse structure and adjusted by forward body bias technique to further reduce supply voltage and power dissipation. The post-layout simulation results demonstrate that the proposed 3.4–10.1[Formula: see text]GHz UWB LNA accomplishes a maximum gain of 14.26[Formula: see text]dB with only 2.33[Formula: see text]mW power consumption at 0.8[Formula: see text]V supply voltage, while Noise Figure (NF) is 1.49–3.41[Formula: see text]dB and the chip area is 0.46[Formula: see text]mm2 including test pads (core area is 0.23[Formula: see text]mm2).

Concurrent 10.5/25 GHz CMOS power amplifier with harmonics and inter‐modulation products suppression

A concurrent 10.5/25 GHz power amplifier (PA) is designed and implemented in a 0.18 μm CMOS technology. This PA employs dual-band matching networks that can suppress harmonics, inter-modulation products, and out-of-band signals so as to improve linearity performances. Moreover, the driver stage of the PA utilises a current-reused topology which increases the gain without increase of the power dissipation. The chip size of the PA is 0.95 × 0.91 mm2 including testing pads, and its power consumption is 150 mW. The PA exhibits a measured gain of 15.2 and 6.8 dB, output P 1dB of 10.5 and 9 dBm, P out,max of 11.4 and 10 dBm and power added efficiency of 9 and 4.8% at 10.5 (f 1) and 25 GHz (f 2), respectively. The measured rejection of signals at 4 GHz (f 2–2f 1), 14.5 GHz (f 2 − f 1) and 21 GHz (2f 1) is 43, 16.5 and 10.8 dB, respectively.

Sub‐harmonic upconversion mixer using 0.18 μm CMOS technology

A novel sub-harmonic upconversion mixer using Chartered 0.18 μm radio-frequency (RF) CMOS technology for 2.4 GHz wireless application is introduced. Using the sub-harmonic technique, the required local oscillator (LO) frequency can be reduced a half, which simplifies the design of the LO. Moreover, the sub-harmonic technique can effectively reduce the influence of LO leakage. The measured results demonstrate that the novel upconversion mixer can provide about 14.4 dB conversion gain, whereas the power consumption is only 1.65 mW with a 1 V supply voltage, and the input-referred third-order intercept point (IIP3) of the mixer is about 4 dBm. The chip area including test pads is only 0.7 × 0.72 mm2.

A Novel Low Voltage Low Power High Linearity Self-biasing Current-reuse Up-conversion Mixer

In this paper, a new complementary metal oxide semiconductor (CMOS) low-voltage low-power current-reuse up-conversion mixer using Chartered $$0.18\,\upmu \hbox {m}$$0.18μm CMOS process for radio frequency transmitter applications is presented. A novel self-biasing current-reuse (SBCR) technique is adopted to achieve more ideal conversion gain (CG) and third-order intermodulation intercept point $$(\hbox {IIP}_{3})$$(IIP3) in the transconductance stage with minimal additional power consumption, which perfects the mixer than conventional Gilbert mixer. As the new SBCR technique employed in the mixer, the post-layout simulation results demonstrate that the SBCR-mixer features about 13 dB CG with 0 dBm local oscillator (LO) power and port-to-port isolation better than 84 dB, while noise figure is 15.66 dB. The $$\hbox {IIP}_{3}$$IIP3 and 1 dB compression point of the mixer are 7.78 dBm and $$-$$-3.76 dBm at 1.41 mW power consumption from a 1 V supply voltage. The chip area is only $$0.70 \times \,0.72\,\hbox {mm}^{2}$$0.70×0.72mm2 even including test pads.

Design and analysis of a 3.1–10.6 GHz UWB low noise amplifier with forward body bias technique

A low power and high gain 3.1–10.6GHz UWB low noise amplifier (LNA) is presented in this paper. The first stage of the UWB LNA employs a resistive shunt feedback topology in conjunction with a parallel LC load to achieve wideband input matching and low noise figure simultaneously. By incorporating the modified current reused cascade configuration and forward body bias technique in the second stage, the proposed UWB LNA can operate at reduced supply voltage and power consumption while maintaining high gain and high reverse isolation. Post-layout simulation results show that the UWB LNA has an average power gain S21 of 14.4dB with gain ripple of ±1.4dB, a high reverse isolation S12 of −83 to −51dB, an input return loss S11 and output return loss S22 of respectively −10.6 to −19.2dB and −12.1 to −16.4dB. An excellent noise figure of 2.2–3.2dB is obtained in the required band with a power dissipation of 9.0mW under a supply voltage of 1.5V. The input 1dB compression point and input third-order intercept point are −15.5dBm and −6.0dBm, respectively, at 6GHz. The chip area including testing pads is only 0.65mm×0.82mm.

Low-voltage, low-power operational transconductance amplifier using novel current-mirrors

ABSTRACTIn this paper, a new complementary metal oxide semiconductor (CMOS) low-voltage, low-power operational transconductance amplifier (OTA) using current-reuse-current- mirror (CRCM) based on chartered 0.18 μm CMOS technology is presented. Because of the new CRCM technique and negative resistance load used in the OTA, the post-layout simulation results demonstrate that the CRCM OTA achieves DC gain of 48.1 dB, gain-bandwidth product of 117 MHz, phase margin of 62°; while the power consumption is only 45.58 μW with ± 0.7 V supply voltages. Moreover, in the current-reuse stage, the passive resistors are replaced by n-channel MOS transistors, which not only make the OTA consists of only active MOS transistors, but also make the DC gain of the OTA can be electronically and continuously controlled by the bias voltage, and the tuning range is from 0 to 48.1 dB. The chip area including test pads is only 0.09×0.12 mm2. The cadence post-layout simulation results are provided to verify all the theoretical analysis.

A Single-chip Highly Efficient CMOS Class-E Power Amplifier for WLAN Applications

This paper presents a class-E, single-ended power amplifier (PA) for WLAN applications. This proposed circuit has a two-stage structure and adopts cascode class-E topology with self-biased technique that avoids using thick-oxide transistors and improves RF performance. The driver employing a current-reused technique can enhance the driving ability and power gain. Additionally, the efficiency is improved by inserting a series LC networks on drain node of switch transistor. The proposed PA is simulated by Advanced Design System (ADS) in TSMC 0.18-μ CMOS technology. With a 2.5-V power supply, the fully integrated CMOS PA achieves 21.5 dBm of maximum output power and 68.3% of power-added efficiency (PAE) at 2.4 GHz. It demonstrates a power gain of 45 dB and gives better output power at minimum input levels. The chip area including testing pads is 0.91 × 0.99 mm2.