In-pixel Signal Processing Research Articles

Highly compact digital pixel structures developed for the CEPC vertex detector

The Circular Electron Positron Collider (CEPC) has been proposed to measure the Higgs properties with a new level of precision. The stringent physics requirements drive a vertex detector constructed with pixel sensors featuring high granularity, fast processing speed and low power dissipation. To explore in-pixel signal processing structures with compact layout size, while maintaining processing speed and low power, a second prototype CMOS pixel sensor, named JadePix-2, has been designed and fabricated in a 0.18μm CMOS image sensor (CIS) process. The prototype contains two versions of digital pixels, both of which have been realized within 22μm pitch size. It operates in the rolling-shutter mode, with processing speed of 100 ns/row and 80 ns/row, respectively, for the two pixel structures. Experimental results show that the total equivalent noise charge (ENC) and power dissipation of the two structures are about 29.5 e− with 6.5 μA/pixel, and 31 e− with 3.7 μA/pixel respectively.

Recent progress in the development of 3D deep n-well CMOS MAPS

In the deep n-well (DNW) monolithic active pixel sensor (MAPS) a full in-pixel signal processing chain is integrated by exploiting the triple well option of a deep submicron CMOS process. This work is concerned with the design and characterization of DNW MAPS fabricated in a vertical integration (3D) CMOS technology. 3D processes can be very effective in overcoming typical limitations of monolithic active pixel sensors. This paper discusses the main features of a new analog processor for DNW MAPS (ApselVI) in view of applications to the SVT Layer0 of the SuperB Factory. It also presents the first experimental results from the test of a DNW MAPS prototype in the GlobalFoundries 130 nm CMOS technology.

Beam test results of different configurations of deep N-well MAPS matrices featuring in pixel full signal processing

We report on further developments of our proposed design approach for a full in-pixel signal processing chain of deep N-well monolithic active pixel sensor, by exploiting the triple well option of a CMOS 130 nm process. Two different geometries of the collecting electrode (namely “Apsel 3 T 1 M 1” and “Apsel 3 T 1 M 2”) was implemented to compare their charge collection efficiency. The results of the characterization of the various versions of pixel matrices with a pion beam of 120 GeV/ c at the SPS H6 CERN facility will be presented. The performances of an “Apsel 3 T 1” chip irradiated with a dose up to 10 Mrad (Co 60) was also measured. Comparison will be presented among the irradiated and the new chip showing the impact of radiation damages on tracking efficiencies.

Deep n-well MAPS in a 130 nm CMOS technology: Beam test results

We report on recent beam test results for the APSEL4D chip, a new deep n-well MAPS prototype with a full in-pixel signal processing chain obtained by exploiting the triple well option of the CMOS 0.13μm process. The APSEL4D chip consists of a 4096 pixel matrix (32 rows and 128 columns) with 50×50μm2 pixel cell area, with custom readout architecture capable of performing data sparsification at pixel level. APSEL4D has been characterized in terms of charge collection efficiency and intrinsic spatial resolution under different conditions of discriminator threshold settings using a 12GeV/c proton beam in the T9 area of the CERN PS. We observe a maximum hit efficiency of 92% and we estimate an intrinsic resolution of about 14μm. The data driven approach of the tracking detector readout chips has been successfully used to demonstrate the possibility to build a Level 1 trigger system based on associative memories. The analysis of the beam test data is critically reviewed along with the characterization of the device under test.

Recent developments in 130 nm CMOS monolithic active pixel detectors

We developed monolithic active pixel detectors, by exploiting the triple well option available in a deep-submicron CMOS process. The novel features are the full analog signal processing and digital functionality implemented at the pixel level. The charge collecting element is realized using the deep N-well (DNW), the full in-pixel signal processing chain includes charge preamplifier, shaper, discriminator and latch. We report on the characterization of the two prototype chips, the first (APSEL0) containing single-channel sensors, with different collecting electrode area, and the latter (APSEL1) with several single pixel structures with improved noise figure implementing also an 8 × 8 matrix of 50 × 50 μm 2 pixel area. So far, the pixel matrix has a simple row by row readout, successfully tested with clock frequency up to 30 MHz. The response of the sensors to infra-red laser, β -rays and soft X-rays (from radioactive sources, 90 Sr and 55 Fe respectively) will be presented. The results achieved so far demonstrate the viability of the technology and suggest new design improvements implemented in the next prototype chips submission (APSEL2).

Development of a triple well CMOS MAPS device with in-pixel signal processing and sparsified readout capabilities

The SLIM5 collaboration has designed, fabricated and tested several prototypes of CMOS Monolithic Active Pixel Sensors (MAPS). The key feature of these devices, with respect to traditional MAPS is to include, at the pixel level, charge amplification and shaping and a first sparsification structure that interfaces with on-chip digital readout circuits. Via the 3-well option of the applied 0.13 μ m ST-Microelectronics CMOS technology each pixel includes a charge preamplifier, a shaper, a discriminator, an output latch, while retaining a fill factor of the sensitive area close to 90%. The last device of the family was submitted on Q4 2006 and the tests are ongoing. On this sensor, an on-chip, off-pixel digital readout block (streamout data sparsification) was added to implement, to control and to readout a test matrix built up of 4 × 4 pixels. It is aimed at proposing solutions that will overcome the readout speed limit of future large-matrix MAPS chips.