Improvement Of Passivation Quality Research Articles

Interfacial energy-band engineering for high open-circuit voltage of rear emitter p-type crystalline silicon solar cells

Rear emitter p-type crystalline silicon (c-Si) tunnel oxide passivating contact (P-TOPCon) devices with low-resistivity (≤1 Ω.cm) c-Si wafer and high-conductivity phosphorus doped (n-type) polysilicon passivating contact (n-poly-Si PC) are expected to achieve high built-in potential (Vbi) and thus open-circuit voltage (Voc). However, the results indicate that the high conductivity of n-poly-Si PC considerably deteriorates the interface passivation quality and lowers the device's Voc. A crucial factor to consider is that the hole and electron can tunnel and recombine together at the c-Si/n-poly-Si PC contact, resulting in a decrease in the quality of interfacial passivation. To inhibit carrier tunnel diffusion and enable energy band engineering at the interface for achieving high Voc, a thin intrinsic poly-Si buffer layer (10 nm) is inserted between SiO2 and n-poly-Si PC. When compared to a device without a buffer, a device with the buffer exhibits a significant improvement in passivation quality and hence Voc. The device with buffer has a Voc of 705 mV and an efficiency of 23.5 %, while that without buffer is 681 mV and 22.6 %, respectively. The introduced buffer has little effect on the industrial manufacturing process, but it does significantly enhance Voc. It has the potential to improve the efficiency of the P-TOPCon devices.

Structural optimization and growth of intrinsic hydrogenated amorphous silicon films by HWCVD

Although the silicon heterojunction (SHJ) solar cell is the crystalline silicon solar cell with highest conversion efficiency at present, its higher cost of production line has been a factor restricting its industrial development. The use of hot wire chemical vapor deposition (HWCVD) technology instead of the mainstream plasma enhanced chemical vapor deposition (PECVD) technology for the deposition of amorphous silicon films can effectively reduce the cost of equipment and processing, and has a bright future. In recent years, i-a-Si:H films grown by PECVD have obtained great improvement in passivation quality, whereas HWCVD technology has been neglected in this field. This has significantly limited the development and application of HWCVD technology in SHJ cell production. In this work, we exploited the differences in the films properties and microstructures deposited by various hot-wire temperatures and successfully developed a structure for the high-passivation-quality i-a-Si:H film grown by HWCVD, consisting of a buffer layer and a double-layer bulk stack. By introducing the buffer layer grown with the 1650 °C hot-wire temperature and pure silane, the effective minority carrier lifetime was improved from 2.3 ms to 7.5 ms, and a cell efficiency enhancement of 0.4%abs was obtained. By depositing the bulk layer sequentially with hot-wire temperatures of 1800 °C and 1900 °C, the passivation quality and the conductance were both improved. An effective minority carrier lifetime of 8 ms and a further cell efficiency enhancement of 0.15%abs were obtained. Finally, SHJ solar cell efficiency of 24.35% was obtained with a home-made HWCVD-based pilot SHJ cell line.

Engineering aluminum oxide/polysilicon hole selective passivated contacts for high efficiency solar cells

Tunnel layer passivated contact technology is already highly efficient in case of selective electron extraction but not as efficient in case of selective hole extraction. Thus far, SiOx/p+-poly-Si contacts have resulted only in efficiencies above ~20.1% for rear-side deployed hole selective contacts. We investigate if hole extraction selectivity can be further improved by substituting the ‘conventionally’ used SiOx tunnel layer exhibiting moderate or even high positive fixed charge density by AlOx tunnel layers, exhibiting high negative fixed charge density. The merits of using atomic layer deposited ultrathin AlOx tunnel layers are investigated and compared with wet chemically formed SiOx tunnel layers to form AlOx/p+-poly-Si and SiOx/p+-poly-Si hole selective passivated contacts respectively. The AlOx thickness (0.13–2 nm) and its thermal budget including annealing time, temperature and ambient were varied. The quality of the resulting AlOx/p+-poly-Si passivated contacts was determined by measuring the recombination current density (Jc) and the effective contact resistivity (ρc). Finally, using the measured values of Jc and ρc, we predict the efficiency potential and selectivity of the passivated contact using Brendel's model. We show that for 425 °C annealed AlOx samples prior to poly-Si capping, there is an improvement in passivation quality due to the high negative AlOx interface charge, which forms only for “thick” tunnel layers (≥1.5 nm). However, after high-temperature poly-Si capping, enhanced boron in-diffusion and charge compensation are degrading the overall passivation quality of “thick” AlOx/p+-poly-Si passivated contacts. The best AlOx/p+-poly-Si passivated contacts use ultra-thin AlOx tunnel layers (efficiency potential of 26.9%), which is only marginally better than the SiOx reference samples, but still improves hole selectivity.

Optimized amorphous silicon nitride layers for the front side passivation of c-Si PERC solar cells

Plasma-enhanced chemical vapour deposition (PECVD) SiNx is the typical choice as anti-reflection coating (ARC) for Silicon based solar cells. However, there still exists a room for improvement in passivation quality of SiNx while maintaining good optics for the front side of a solar cell. In this paper, we studied in detail the optical and electrical properties of SiNx layers by varying the chamber pressure and substrate temperature in an industrially used inline PECVD tool. Both the optical as well as electrical properties of SiNx layers were found to be significantly influenced by the chamber pressure and substrate temperature. A trade-off between excellent optics and low surface recombination is observed with an increase in chamber pressure, whereas higher substrate temperature generally led to better passivation quality. The Si-H bond density, which is expected to directly influence the quality of surface passivation, increased at high pressure and at low substrate temperature. Based on our investigations, a good compromise between optics and surface passivation is struck to prepare optimized SiNx layers and apply them as passivation layers for the front side of passivated emitter and rear cell (PERC) solar cells. The best solar cells show high short-circuit current density (jSC) of 39.9 mA/cm2 corresponding to the SiNx layers with low parasitic absorption, good antireflection property, and excellent passivation of the surface and bulk silicon. The current-voltage (I-V) results are found to be in agreement with internal quantum efficiency (IQE) measurements of the solar cells.

Single material TiO2 thin film by atomic layer deposition for antireflection and surface passivation applications on p-type c-Si

A thin film deposited on the front surface of solar cell plays an important role in reducing the reflection of incident light and providing surface passivation. Although ultrathin TiO2 films have shown excellent performance of surface passivation, simultaneously serving both functions is hindered by the crystallization issue, which can degrade the passivation quality of TiO2 film, as the film thickness is over certain value (few nanometer only). Here we showed that both functions can be satisfied by single material of titanium oxide film through atomic layer deposition at low temperatures. By varying deposition temperatures from 80 to 200 °C, the TiO2 film deposited at 80 °C can maintain its amorphous phase up to the thickness of 114 nm. In addition, the optimal thickness for antireflection calculated by OPAL 2 is 61 nm, meaning that amorphous TiO2 film to provide antireflection and surface passivation can be achieved. The passivation quality is verified by minority carrier lifetime measurement using photo-conductance decay method and presented the ultralow surface recombination velocity of 8.7 cm/s. Furthermore, the passivation mechanism is investigated by X-ray diffraction (XRD) and secondary ion mass spectroscopy (SIMS), in which the absence of crystalline issue is confirm and both chemical passivation (due to H termination) and field effect passivation (due to residual Cl atoms) are associated with the improvement of passivation quality. A post deposition anneal is conducted on the TiO2 film deposited at 80 °C. The results present that extra thermal budgets can ruin the passivation quality, which is explicated by the TiO2 crystallization as the temperature exceeding 350 °C from the XRD measurements, and by the descending of Cl atom (also field effect passivation) as increasing of the annealing temperature from the SIMS measurements.

Silicon surface passivation using thin HfO2 films by atomic layer deposition

Hafnium oxide (HfO2) is a potential material for equivalent oxide thickness (EOT) scaling in microelectronics; however, its surface passivation properties particularly on silicon are not well explored. This paper reports investigation on passivation properties of thermally deposited thin HfO2 films by atomic layer deposition system (ALD) on silicon surface. As-deposited pristine film (∼8nm) shows better passivation with <100cm/s surface recombination velocity (SRV) vis-à-vis thicker films. Further improvement in passivation quality is achieved with annealing at 400°C for 10min where the SRV reduces to ∼20cm/s. Conductance measurements show that the interface defect density (Dit) increases with film thickness whereas its value decreases after annealing. XRR data corroborate with the observations made by FTIR and SRV data.

Improvement in passivation quality and open-circuit voltage in silicon heterojunction solar cells by the catalytic doping of phosphorus atoms

We apply phosphorus (P) doping to amorphous silicon (a-Si)/crystalline silicon (c-Si) heterojunction solar cells realized by exposing c-Si to P-related radicals generated by the catalytic cracking of PH3 molecules (Cat-doping). An ultrathin n+-layer formed by P Cat-doping acts to improve the effective minority carrier lifetime (τeff) and implied open-circuit voltage (implied Voc) owing to its field effect by which minority holes are sent back from an a-Si/c-Si interface. An a-Si/c-Si heterojunction solar cell with a P Cat-doped layer shows better solar cell performance, particularly in Voc, than the cell without P Cat-doping. This result demonstrates the feasibility of applying Cat-doping to a-Si/c-Si heterojunction solar cells, owing to the advantage of the low-temperature (<200 °C) process of Cat-doping.

Effect of hydrogen on passivation quality of SiNx/Si-rich SiNx stacked layers deposited by catalytic chemical vapor deposition on c-Si wafers

We investigate the role of hydrogen content and fixed charges of catalytic chemical vapor deposited (Cat-CVD) SiNx/Si-rich SiNx stacked layers on the quality of crystalline silicon (c-Si) surface passivation. Calculated density of fixed charges is on the order of 1012cm−2, which is high enough for effective field effect passivation. Hydrogen content in the films is also found to contribute significantly to improvement in passivation quality of the stacked layers. Furthermore, Si-rich SiNx films deposited with H2 dilution show better passivation quality of SiNx/Si-rich SiNx stacked layers than those prepared without H2 dilution. Effective minority carrier lifetime (τeff) in c-Si passivated by SiNx/Si-rich SiNx stacked layers is as high as 5.1ms when H2 is added during Si-rich SiNx deposition, which is much higher than the case of using Si-rich SiNx films prepared without H2 dilution showing τeff of 3.3ms.

Simple Cleaning and Conditioning of Silicon Surfaces with UV/Ozone Sources

Within this paper the applicability of three methods to clean and condition the surface of silicon wafers by an ultra-thin oxide layer were tested: two UV/O3 sources (an Hg vapor lamp and a high efficiency excimer module) as well as a wet chemical oxidation in HNO3.It has been demonstrated that organic residues resulting from wafering and masking the surface during alkaline texturing can be removed by UV/O3 (Hg vapor lamp) exposure. Moreover the use of UV/O3 (excimer) and HNO3 oxides result in an improvement of passivation quality and emitter saturation current in combination with Al2O3/SiNx or AlN/SiNx passivation stacks. For n-type silicon wafers with a 70Ω/sq. boron emitter and Al2O3/SiNx passivation very low j0e values of 49 fA/cm2 are achieved by conditioning with UV/O3 or HNO3.Another important application of ultra-thin SiOx layers is as tunnel oxides for the rear side of the TOPCon (Tunnel Oxide Passivated Contact) cell concept [1,2]. High iVOC values exceeding 720mV on planar samples and 710mV on textured samples are obtained with UV/O3 grown tunnel oxides after annealing. The structural properties of the SiOx layers that were analyzed by XPS and compared to the iVOC data, indicate that a minimum oxide layer thickness of approx. 1.4nm and a high amount of oxygen rich sub oxides species (Si2O3, close to the structure of stoichiometric SiO2) are required to obtain a good interface passivation stable up to annealing temperatures of 900°C.

Improving the performance of amorphous and crystalline silicon heterojunction solar cells by monitoring surface passivation

The influence of thermal annealing on the crystalline silicon surface passivating properties of selected amorphous silicon containing layer stacks (including intrinsic and doped films), as well as the correlation with silicon heterojunction solar cell performance has been investigated. All samples have been isochronally annealed for 1h in an N2 ambient at temperatures between 150°C and 300°C in incremental steps of 15°C. For intrinsic films and intrinsic/n-type stacks, an improvement in passivation quality is observed up to 255°C and 270°C, respectively, and a deterioration at higher temperatures. For intrinsic/n-type a-Si:H layer stacks, a maximum minority carrier lifetime of 13.3ms at an injection level of 1015cm−3 has been measured. In contrast, for intrinsic/p-type a-Si:H layer stacks, a deterioration in passivation is observed upon annealing over the whole temperature range. Comparing the lifetime values and trends for the different layer stacks to the performance of the corresponding cells, it is inferred that the intrinsic/p-layer stack is limiting device performance. Furthermore, thermal annealing of p-type layers should be avoided entirely. We therefore propose an adapted processing sequence, leading to a substantial improvement in efficiency to 16.7%, well above the efficiency of 15.8% obtained with the ‘standard’ processing sequence.