Adjacent Channel Leakage Ratio Improvement Research Articles

Efficient Digital Predistortion Using Sparse Neural Network

This paper proposes an efficient neural-network-based digital predistortion (DPD), named as envelope time-delay neural network (ETDNN) DPD. The method complies with the physical characteristics of radio-frequency (RF) power amplifiers (PAs) and uses a more compact DPD model than the conventional neural-network-based DPD. Additionally, a structured pruning technique is presented and used to reduce the computational complexity. It is shown that the resulting ETDNN obtained after applying pruning becomes so sparse that its complexity is comparable to that of conventional DPDs such as memory polynomial(MP) and generalized memory polynomial (GMP), while the degradation in performance due to the pruning is negligible. In an experiment on a 3.5-GHz GaN Doherty power amplifier (PA), our method with the proposed pruning had only one-thirtieth the computational complexity of the conventional neural-network-based DPD for the same adjacent channel leakage ratio (ACLR). Moreover, compared with memory-polynomial-based digital predistortion, our method with the proposed pruning achieved a 7-dB improvement in ACLR, despite it having lower computational complexity.

Analysis on predistortion algorithm for improving adjacent channel leakage ratio of radio over fiber systems

AbstractNonlinear distortion introduced by optoelectronic components imposes serious limitations on the performance of radio over fiber (RoF) systems, such as dynamic range and adjacent channel leakage ratio (ACLR). In this article, we focus on the impact of digital predistortion (DPD) on the ACLR improvement in a wideband RoF system with multiple carriers. Three key factors, that is, the order of DPD algorithm, the initial phases of carriers, and the processing bandwidth of the predistortion module, are all taken into account in investigating the influence of predistortion on the ACLR performance of RoF systems. A preliminary experiment verifies the effectiveness of predistortion technique for improving the ACLR performance. Quantitative simulation results demonstrate that with the increase in the order of DPD algorithm, the ACLR performance can be significantly improved while the phase randomness within 10 carriers leads to an ACLR fluctuation up to 5 dB. The dependence of the ACLR improvement on the processing bandwidth of the predistortion module, which is very important in practical application, has also been quantitatively studied.

Impact evaluation of DC operating condition on DPD linearizability and power efficiency in GaN-based power amplifiers

AbstractThe paper presents the results of studies on the effect of transistor DC operating conditions on GaN power amplifiers’ (PAs) power efficiency and linearity improved by digital predistortion (DPD). The single-ended 10 W (ISM2.45 GHz) and 150 W (3.4/3.6 GHz) GaN HEMT PAs excited by wideband LTE20 E-TM1.1 signal were tested. To check the applicability of the small-signal approach for designing of LTE signals’ PAs, the 150 W PA using transistor model extracted from S-parameters measured at the properly selected operating points was designed. The conventional DPD based on the indirect learning architecture and the memory polynomial model of PA non-linearity was implemented. The results of the research show that in case of class A and B PAs operating up to several dozen watts, an additional improvement in adjacent channel leakage ratio (ACLR) of the order of a few dB only by an increase in the quiescent drain current of PA transistor can be achieved. However, a noticeable ACLR improvement with a coincident increase in power-added efficiency (PAE) can be obtained by choosing the compromise DC operating point and using DPD. In the case of high-PAs, the linearity and efficiency are strongly dependent on the load of a transistor, thus the role of DPD is significantly increased.

A low-power high-performance digital predistorter for wideband power amplifiers

In this paper, we present a low-power high-performance digital predistorter (DPD) for the linearization of wideband RF power amplifiers (PAs). It is based on the novel FIR memory polynomial (FIR-MP) predistorter model, which significantly augments the performance of the conventional memory polynomial predistorter with the use of complex baseband digital FIR filter prior to the memory polynomial. The adjacent channel leakage ratio (ACLR) performance comparison between the conventional MP and the proposed FIR-MP is done based on simulations with multi-carrier modulated signals of 20 and 80 MHz bandwidths. The PA models used for the simulations are extracted from the measurements of a commercial $$1\,\hbox {W}$$ GaAs HBT PA. At the ideal system-level simulations, the improvements in ACLR over the conventional MP are 7.2 and 15.6 dB, respectively, for 20 and 80 MHz signals. The choice of selection of various parameters of the predistorter along with the subsequent digital-to-analog converter (DAC) is presented. The impact of fixed-point representation is assessed using ACLR metrics, which shows that a wordlength of 14 bits is sufficient to obtain ACLR beyond $$45\,\hbox {dBc}$$ with a margin of $$10\,\hbox {dB}$$ . The proposed predistorter is synthesized in $$28\,\hbox {nm}$$ fully-depleted silicon-on-insulator (FDSOI) CMOS process. It is shown that with a fraction of the power and die area of that of the MP a huge improvement in ACLR is attained. With an overall power consumption of 8.2 and 88.8 mW, respectively, for 20 and 80 MHz signals, the FIR-MP DPD proves to be a suitable candidate for small-cell base station PA linearization.

Wide-Bandwidth and High-Linearity Envelope- Tracking Front-End Module for LTE-A Carrier Aggregation Applications

The envelope-tracking front-end module (ETFEM) consisting of an envelope-tracking supply modulator (ETSM), a dual-power-mode power amplifier (PA), and a single-pole-double-throw (SPDT) switch is proposed for the Long-Term Evolution-Advanced (LTE-A) intraband carrier aggregation (CA) signal. The linear stage of ETSM is implemented by introducing the dual-path crossover current-reuse mechanism to obtain the measured efficiency 79.6%, 76.4%, 74%, and 72.8% for 7.4-, 9.6-, 11.2-, and 12.3-dB peak-to-average-power ratio (PAPR) 16-QAM LTE-A CA signals with $1 \times 20$ , $2 \times 20$ , $3 \times 20$ , and $4 \times 20$ MHz bandwidths, respectively. A SiGe BiCMOS dual-power-mode PA with two output power modes is realized and incorporated with ETSM to improve the adjacent channel leakage ratio (ACLR) by 11.7, 7.9, and 4.7 dB and the error vector magnitude (EVM) by 7.1%, 6.1%, and 4.1% at 26.8-, 24.3-, and 21.7-dBm output powers for the LTE-A 16-QAM signals with $1 \times 20$ , $2 \times 20$ , and $3 \times 20$ MHz bandwidths at 1.95 GHz, respectively. The SPDT switch integrated with ETSM provides 0.3-dB power loss reduction, 1.1-dB ACLR improvement, and 0.7% EVM enhancement at 12-dBm average input power. The ETFEM operated at 12.5-dB PAPR 64-QAM LTE-A CA signal with $4 \times 20$ MHz bandwidth demonstrates that the improvements of 1.3-dB ACLR and 1% EVM at 13.1-dBm output power are achieved for the wide-bandwidth and high-linearity FEM applications.

Application of the NARX neural network as a digital predistortion technique for linearizing microwave power amplifiers

ABSTRACTThis work presents a digital predistortion (DPD) scheme to linearize power amplifiers (PAs) using a recurrent neural network called Nonlinear AutoRegressive with eXogenous input model (NARX) neural network (NARXNN). The architecture of the NARXNN is based on a class of discrete‐time nonlinear system named NARX. Its topology has embedded memory at the input and output of the neural architecture, which allows an efficient linearization of PAs. To show the benefits of the DPD with NARXNN, a commercial PA is fed with a long term evolution signal at 2.0 GHz with 10 MHz of bandwidth. Our experimental results show an adjacent channel leakage ratio improvement of 24 dB. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:2137–2142, 2015

A New Digital Predistortion for Wideband Power Amplifiers With Constrained Feedback Bandwidth

This letter presents a new digital predistortion (DPD) solution for wideband power amplifiers (PAs) with restricted feedback bandwidth and relatively low sampling rate. By integrating a microwave cavity filter into the feedback path, the feedback bandwidth is reduced efficiently. A PA parameter extraction method is then proposed to identify the PA model, using the bandwidth-constrained signals. By applying the extracted parameters to the direct learning architecture, the DPD function can be obtained, which can linearize nonlinear distortion over the sampling bandwidth. Experiments demonstrate that a 22 dB adjacent channel leakage ratio improvement is acquired for a 100 MHz Long Term Evolution-advanced signal, even when the feedback bandwidth is restricted from 500 MHz to 100 MHz, which remarkably reduces the ADC sampling rate from 1105.92 Msps to 368.64 Msps.

The Dynamic Behavioral Model of RF Power Amplifiers With the Modified ANFIS

The adaptive neuro-fuzzy inference system (ANFIS) has been widely used for modeling different kinds of nonlinear systems including RF power amplifiers (PAs). The modified ANFIS (MANFIS) architecture is simpler than that of ANFIS, but with nearly the same performance for modeling nonlinear systems. In this paper, the MANFIS is applied to model RF PAs with memory effects. The simulation and experimental results both in the time and frequency domains show that this model has good modeling accuracy and the characteristics of faster convergence and lower computational complexity compared with the ANFIS model. The normalized mean squared errors of the MANFIS model are slightly lower than those of some other neural network models such as the real-valued time delay neural network, radial basis-function neural network, etc. Finally, the MANFIS model is successfully used in a digital predistortion system, which can provide over 10- dB adjacent channel leakage ratio improvement for three-carrier wideband code division multiple access signals.

High-Power Amplifier Linearization Using the Doherty Amplifier as a Predistortion Circuit

This paper presents the application of a Doherty power amplifier (DPA) as a predistortion circuit for the linearization of high PA. When the DPA is employed as the driver amplifier, its nonlinearity is used as predistorted components to cancel the strong nonlinearity of the main amplifier. To verify the proposed method, the DPA is implemented with two 30-W silicon metal-oxide semiconductor field-effect transistors and tested with a 180-W main amplifier at a wideband code-division multiple access (WCDMA) band of 2.14 GHz. For a two-tone signal with 2-MHz tone spacing and a one-carrier WCDMA signal, the significant cancellation of the third- and fifth-order intermodulation (IM3 and IM5) components and a superior adjacent channel leakage ratio improvement are achieved.

Highly Linear Predistortion Power Amplifiers With Phase-Controlled Error Generator

A simple predistortion technique to cancel the fifth-order intermodulation (IM5) as well as third-order intermodulation (IM3) components using a third-order predistorter (PD) is represented. The IM3 and IM5 components are cancelled out simultaneously by their same magnitude and phase difference in the PD and power amplifier (PA). Moreover, this phase difference is controlled by using the phase-controlled error generator in the PD. For experimental verification, a third-order PD has been implemented and tested in a 30-W class-AB PA at the wide-band code division multiple access (WCDMA) band of 2.11-2.17GHz. Two-tone test results show that significant cancellation of the IM3 and IM5 components can be obtained. For a four-carrier WCDMA application, significant adjacent channel leakage ratio improvement is achieved over a wide range of output power levels

Linearity optimization of a high power Doherty amplifier based on post-distortion compensation

The linearity of a 30-W high-power Doherty amplifier is optimized using post-distortion compensation. A balanced high-power Doherty amplifier using two push-pull laterally-diffused metal-oxide semiconductor (LDMOS) field-effect transistors (FETs) is linearized by optimum adjustment of the peaking compensation line, shunt capacitors, and gate biases. The measured results of an optimized Doherty amplifier for a four-carrier wideband code division multiple access (W-CDMA) signal, achieved -43 dBc adjacent channel leakage ratio (ACLR) at a /spl plusmn/5 MHz offset frequency. This is an ACLR improvement of 12.2dB and 6.5dB in comparison to the Doherty amplifier before optimization and a ClassAB amplifier, respectively.