Implemented Fault Injection Research Articles

Using Fault Injection to Assess Blockchain Systems in Presence of Faulty Smart Contracts

Blockchain has become particularly popular due to its promise to support business-critical services in very different domains (e.g., retail, supply chains, healthcare). Blockchain systems rely on complex middleware, like Ethereum or Hyperledger Fabric, that allow running smart contracts, which specify business logic in cooperative applications. The presence of software defects or faults in these contracts has notably been the cause of failures, including severe security problems. In this paper, we use a software implemented fault injection (SWIFI) technique to assess the behavior of permissioned blockchain systems in the presence of faulty smart contracts. We emulate the occurrence of general software faults (e.g., missing variable initialization) and also blockchain-specific software faults (e.g., missing require statement on transaction sender) in smart contracts code to observe the impact on the overall system dependability (i.e., reliability and integrity). We also study the effectiveness of formal verification (i.e., done by solc-verify) and runtime protections (e.g., using the assert statement) mechanisms in detection of injected faults. Results indicate that formal verification as well as additional runtime protections have to complement built-in platform checks to guarantee the proper dependability of blockchain systems and applications. The work presented in this paper allows smart contract developers to become aware of possible faults in smart contracts and to understand the impact of their presence. It also provides valuable information for middleware developers to improve the behavior (e.g., overall fault tolerance) of their systems.

A Fault Injection System Based on QEMU Simulator and Designed for BIT Software Testing

An important step in the development of dependable systems is the validation of their fault tolerance properties. Fault injection has been widely used for this purpose. This paper presents a simulator implemented fault injection and monitoring environment based on the QEMU platform, called BitVaSim, which is targeted for the embedded development boards equipped with PowerPC or ARM processor together with Built-In Test software operating environment.BitVaSim takes advantage of simulation and do no harm or irruption to either the real hardware or the software, in addition, all the simulated parts are reachable so that more fault modes are available to achieve.BitVaSim uses abstract key-value pairs to describe the functional fault modes, and then simulates the hardware board as while as realistic faults incurred by hardware into the simulator, in order to monitor the activation of the faults and their impact on the target system especially the BIT system behavior in detail. Fault injection interfaces are configured to implement failure mode matching and fault conditions triggering to inject faults on demand in simulator runtime.Faults injected by BitVaSim can affect any process running on the target system (including the kernel), and it is possible to inject faults in applications for which the source code is not available.Experimental results are presented to demonstrate the accuracy and potential of BitVaSim in the evaluation of the dependability properties of the complex computer systems and the BIT system.

XML schema based fault set definition to improve fault injection tools interoperability

Software implemented fault injection tools (SWIFI) use fault injectors to carry out the fault injection campaign defined in a GUI-based application. However, the communication between the fault injector and the application is defined in an ad-hoc manner. This paper describes an XML schema formalisation approach for the definition of fault sets which specify low level memory and/or register value corruptions in embedded microprocessor-based systems and resource usage faults in host based systems. Through this proposed XML schema definition, different injectors could be used to carry out the same fault set injection. To validate this approach an experimental tool called Exhaustif®, consisting of a GUI Java application for defining the fault sets and injection policies, one injector for Windows hosts systems and two injectors for Sparc and i386 architectures under RTEMS have been developed.

Error Detection Enhancement in PowerPC Architecture-based Embedded Processors

This paper presents a behavior-based error detection technique called Control Flow Checking using Branch Trace Exceptions for PowerPC processors family (CFCBTE). This technique is based on the branch trace exception feature available in the PowerPC processors family for debugging purposes. This technique traces the target addresses of program branches at run-time and compares them with reference target addresses to detect possible violations caused by transient faults. The reference target addresses are derived by a preprocessor from the source program. To enhance the error detection coverage, three other mechanisms, i.e., Machine Check Exception, System Trap Instructions and Work Load Timer are combined with the Branch Trace Exception mechanism. The proposed technique is experimentally evaluated on a 32-bit PowerPC microcontroller using software implemented fault injection (SWIFI) and Power Supply Disturbances fault injection (PSD). A total of 6,000 faults were injected in microcontroller to measure the error detection coverage of the proposed control flow checking technique. The experimental results show that this technique detects about 95.2% of transient errors in software implemented fault injection method and 96.4% of transient errors in power supply disturbances fault injection method.

Embedded system dependability evaluation with simulation tools

Dependability evaluation is an important issue in designing and exploiting embedded systems. The paper presents the capabilities and limitations of fault injection techniques in relevance to dependability analysis. e discuss the impact of fault models on the simulation results and their interpretation. A special attention is paid to transient faults, which dominate in contemporary systems. The presented analysis bases mostly on our experience with software implemented fault injection. As an illustration we give some original experimental results for a real application.

Web Service Based Software Implemented Fault Injection

Web Service Based Software Implemented Fault Injection

Error Detection Enhancement in COTS Superscalar Processors with Performance Monitoring Features

Increasing use of commercial off-the-shelf (COTS) superscalar processors in industrial, embedded, and real-time systems necessitates the development of error detection mechanisms for such systems. This shows an error detection scheme called committed instructions counting (CIC) to increase error detection in such systems. The scheme uses internal performance monitoring features and an external watchdog processor (WDP). The performance monitoring features enable counting the number of committed instructions in a program. The scheme is experimentally evaluated on a 32-bit Pentium/spl reg/ processor using software implemented fault injection (SWIFI). A total of 8181 errors were injected into the Pentium/spl reg/ processor. The results show that the error detection coverage varies between to 90.92% and 98.41%, for different workloads.

Empaquetâches de tolérance aux fautes pour les systèmes temps réel

The integration of software COTS components into safety-critical real-time systems raises serious problems from a dependability viewpoint. Wrappers can be used to assist such an integration by providing additional error detection mechanisms. We recently defined a framework to automatically develop such a type of wrappers from temporal logic specifications. In this paper, we extend this framework to endow wrappers with forward error recovery capabilities based on the concept of recovery actions. Recovery actions consist of variants of basic functions of the target system that are run concurrently to help correct errors. We apply these comprehensive wrappers to a real-time COTS microkernel. Software implemented fault injection (SWIFI) is then used to evaluate the efficiency of the wrappers. This step helped identify the sets of wrappers that maximize the error detection and recovery coverage while meeting hard task deadlines.