Implementation Of Signal Processing Algorithms Research Articles

Smartphone-Based Real-Time Digital Signal Processing, Third Edition

Real-time or applied digital signal processing courses are offered as follow-ups to conventional or theory-oriented digital signal processing courses in many engineering programs for the purpose of teaching students the technical know-how for putting signal processing algorithms or theory into practical use. These courses normally involve access to a teaching laboratory that is equipped with hardware boards, in particular DSP boards, together with their supporting software. A number of textbooks have been written discussing how to achieve real-time implementation on these hardware boards. This book discusses how to use smartphones as hardware boards for real-time implementation of signal processing algorithms, thus providing an alternative to the hardware boards that are used in signal processing laboratory courses. The fact that mobile devices, in particular smartphones, have become powerful processing platforms led to the development of this book to enable students to use their own smartphones to run signal processing algorithms in real-time considering that these days nearly all students possess smartphones. Changing the hardware platforms that are currently used in applied or real-time signal processing courses to smartphones creates a truly flexible laboratory experience or environment for students. In addition, it relieves the cost burden associated with using dedicated signal processing boards noting that the software development tools for smartphones are free of charge and are well-maintained by smartphone manufacturers. This book is written in such a way that it can be used as a textbook for real-time or applied digital signal processing courses offered at many universities. Ten lab experiments that are commonly encountered in such courses are covered in the book. It is written primarily for those who are already familiar with signal processing concepts and are interested in their real-time and practical aspects. Similar to existing real-time courses, knowledge of C programming is assumed. This book can also be used as a self-study guide for those who wish to become familiar with signal processing app development on either Android or iOS smartphones/tablets. A zipped file of the codes discussed in the book can be acquired from this third-party website: http://sites.fastspring.com/bookcodes/product/SignalProcessingBookcodesThirdEdition

Quantization in Compressive Sensing: A Signal Processing Approach

The influence of finite-length registers and the corresponding quantization effects on the reconstruction of sparse and approximately sparse signals from a reduced set of measurements is analyzed in this paper. For the nonquantized measurements, the compressive sensing (CS) framework provides highly accurate reconstruction algorithms that produce negligible errors when the reconstruction conditions are met. However, hardware implementations of signal processing algorithms inevitably involve finite-length registers and quantization of the measurements. A detailed analysis of the effects related to the measurement quantization, with an arbitrary number of bits, is provided in this paper. A unified novel mathematical model to characterize the influence of the quantization noise and the signal nonsparsity on the CS reconstruction is introduced. Using this model, an exact formula for the expected error energy in the CS-based reconstructed signal is derived, while in the literature its bounds have been reported only. The theory is validated through various numerical examples with quantized measurements, involving scenarios with approximately sparse signals, noise folding effect, and floating-point arithmetics.

Architecture of the reconfigurable ultrasonic system‐on‐chip hardware platform

Design of ultrasonic signal processing systems requires a paradigm shift to fully utilise the benefits of recent advancements in the field of integrated circuits. It is necessary to design a standardised common platform that provides the flexibility to develop both software and hardware solutions. This enables the user to explore the full design space including software only, hardware only, and hardware/software co-design. To fulfil this purpose, the authors introduce the reconfigurable ultrasonic system-on-chip hardware (RUSH) platform. RUSH provides a common basis which significantly reduces the effort required to develop an ultrasonic signal processing system able to process the full range of ultrasound from 20 kHz to 20 MHz. Furthermore, this study aims to make the design and implementation of signal processing algorithms in embedded software and reconfigurable hardware very efficient. To demonstrate the computational efficiency and design flexibility of the RUSH platform, several important computationally intense algorithms such as split spectrum processing, chirplet signal decomposition and coherent averaging have been successfully ported to the RUSH platform, emphasising the many parts of the RUSH architecture.

FMCW 전파고도계의 신호처리 알고리즘 구현

FMCW 전파고도계의 신호처리 알고리즘 구현

VDMOS electrical parameters potentially usable as mechanical state indicators for power VDMOS assemblies

Power device reliability is a multidisciplinary domain. It requires design and integration of sensors, implementation of signal processing algorithms that allow processing the different data provided by the different sensors in order to predict by statistical means the device failure occurrence and consequently anticipate the power device replacement. Currently, for device ageing studies in a laboratory, electrical measurements of device parameters are often used as an indicator of device ageing. Furthermore, smart metal-oxide semi-conductor technology integrates more and more sensors that permit to measure quantities such as on-state resistance or junction temperature of the device. In power vertical diffused metal oxide semiconductor (VDMOS) assemblies, it would be interesting to make use of the VDMOS electrical parameters deviations in order to monitor the ageing state of the power assembly. To that end, we carry-out in this paper a study mainly based upon electro-thermo-mechanical simulations in order to identify the power VDMOS electrical parameters that could be monitored in order to access to the mechanical state of the power assembly and therefore anticipate the assembly failure. The power VDMOS R on as well as zero temperature coefficient (ZTC) point are of interest because they are sensitive to mechanical stress. Consequently, in this paper, a procedure to minimise temperature impact on the Ron of the VDMOS transistor such that one could use the Ron as mechanical state indicator is shown. Another solution that makes use of a specific operating point of VDMOS (ZTC) which is temperature independent is also studied by simulations and experiment.

Hardware-accelerated design space exploration framework for communication systems

The efficient hardware implementation of signal processing algorithms requires a rigid characterization of the interdependencies between system parameters and hardware costs. Pure software simulation of bit-true implementations of algorithms with high computational complexity is prohibitive because of the excessive runtime. Therefore, we present a field-programmable gate array (FPGA) based hybrid hardware-in-the-loop design space exploration (DSE) framework combining high-level tools (e.g. MATLAB, C++) with a System-on-Chip (SoC) template mapped on FPGA-based emulation systems. This combination significantly accelerates the design process and characterization of highly optimized hardware modules. Furthermore, the approach helps to quantify the interdependencies between system parameters and hardware costs. The achievable emulation speedup using bit-true hardware modules is a key enabling the optimization of complex signal processing systems using Monte Carlo approaches which are infeasible for pure software simulation due to the large required stimuli sets. The framework supports a divide-and-conquer approach through a flexible partitioning of complex algorithms across the system resources on different layers of abstraction. This facilitates to efficiently split the design process among different teams. The presented framework comprises a generic state of the art SoC infrastructure template, a transparent communication layer including MATLAB and hardware interfaces, module wrappers and DSE facilities. The hardware template is synthesizable for a variety of FPGA-based platforms. Implementation and DSE results for two case studies from the different application fields of synthetic aperture radar image processing and interference alignment in communication systems are presented.

HIGH THROUGHPUT FILTER ARCHITECTURE FOR OPTIMAL FPGA-BASED IMPLEMENTATIONS

Modern field programmable gate arrays (FPGAs) offer built in support for efficient implementation of signal processing algorithms in the form of specialized embedded blocks such as high speed carry chains, specialized shift registers, adders, multiply accumulators (MAC) and block memories. These dedicated elements provide increased computational power and are used for efficient implementation of computationally extensive algorithms. This paper proposes a novel algorithm and architecture for the design and implementation of high performance intermediate frequency (IF) filters on FPGAs. In this research, we have proposed innovative design methodologies for generation of optimal feed forward and recursive architectures to be mapped on a family of FPGAs. Keeping in perspective the limited number of registers within the embedded blocks, the new methodology applies transformations to achieve higher throughput by applying various optimizations to the design algorithm. Implementation options include systolic MAC, transpose direct form MAC, canonic signed digit and distributed arithmetic based filters to suite the most economical FPGA implementation. The paper demonstrates the methodology and shows its applicability by synthesizing the designs and comparing the results to a number of traditional architectures and intellectual property cores. Using Xilinx Virtex-5 FPGA, our results show a throughput improvement between 7% and 30% with an average improvement of 16% over traditional implementations of these designs.

Multicore implementation of a fixed-complexity tree-search detector for MIMO communications

Multicore systems allow the efficient implementation of signal processing algorithms for communication systems due to their high parallel processing capabilities. In this paper, we present a high-throughput multicore implementation of a fixed-complexity tree-search-based detector interesting for MIMO wireless communication systems. Experimental results confirm that this implementation allows to accelerate the data detection stage for different constellation sizes and number of subcarriers.

An efficient GPU implementation of fixed-complexity sphere decoders for MIMO wireless systems

The use of many-core processors such as general purpose Graphic Processing Units (GPUs) has recently become attractive for the efficient implementation of signal processing algorithms for communication systems. This is due to the cost-effectiveness o

Use of a Variable Wordlength Technique in an OFDM Receiver to Reduce Energy Dissipation

Wordlength determination is an indispensable task in digital hardware implementations of signal processing algorithms because the wordlength affects power consumption and system performance. There is a tradeoff between power consumption and system performance when searching for the optimum wordlength. We have developed a technique of dynamically controlling the wordlength used in the signal processing algorithms of wireless orthogonal frequency-division multiplexing (OFDM) receivers. The receiver dynamically changes the wordlength on the basis of the conditions in the propagation environment while satisfying the user-required communication quality. That is, the system optimizes the wordlength while operating by sensing its own performance and gradually adjusting this wordlength to improve performance. Testing revealed that, for a packet error rate (PER) of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> , the application of this technique to an OFDM receiver reduces energy dissipation by 18.1%-30.2%.

Implementation of signal processing algorithms for 3G and beyond

For communication systems of third generation and beyond, the algorithmic complexity will increase significantly compared with 2G and 2.5G systems, as we can see from the example of channel estimation. The answer to these demands will consist of transceivers with re-configurable hardware accelerators in advanced CMOS technology.

Automatic derivation and implementation of signal processing algorithms

We present a computer algebra framework to automatically derive and implement algorithms for digital signal processing. The two main parts of the framework are AREP, a library for symbolic manipulation of group representations and structured matrices, and SPL, a compiler turning matrix expressions into efficient imperative-style numerical programs.

A universal nonlinear component and its application to WSI

Presents a high-speed multifunction chip for performing one of four nonlinear operations: 1) square root, 2) reciprocal, 3) sine/cosine, and 4) arctangent. Each of these functions is evaluated with one ROM access, two additions, and one major and one minor multiplication, yielding a new result every two clock cycles. Its performance signifies an estimated three-to-four-fold increase in speed (for comparable technologies and minimum feature size) over existing approaches. Furthermore, since all four functions are performed on the same cell, a silicon-area advantage of approximately three is realized when the application demands multiple functions. In wafer scale integration (WSI) of signal and image processing algorithms, several such functions are usually needed, while defect tolerance dictates the use of just one or two types of cells. Thus the new component is ideally suited for monolithic WSI. However, it can also be used as a co-processor/accelerator for commercial DSP chips in hybrid WSI implementation of signal processing algorithms. The underlying principle, which has made the combined goals of high-speed and multifunctionality possible, is second-order interpolation of very small ROM tables. Two versions are presented: a 24-b chip, and a 16-b chip, both fabricated in 2.0- mu m CMOS technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Pipelining in algorithms with quantizer loops

High-speed implementation of signal processing algorithms for digital transmission is addressed. The internal feedback or recursion in these algorithms makes it difficult to implement recursive systems concurrently using either pipelining or parallelism. In the past, look-ahead computation techniques were successfully applied to create necessary concurrency in linear recursive and some nonlinear recursive operations (such as the add-compare-select operation). Novel computation approaches are proposed, and the look-ahead technique is extended to pipeline the feedback loops containing finite-level quantizers. Approaches to pipeline piecewise-linear recursive systems are presented. The proposed architectures are suitable for real-time high-speed implementation of quantizer loop operations where the levels of quantizer and the order of the loops are small. >

Single-chip 2-port adaptors for wave digital filters

In recent years, systolic arrays have been widely used for the implementation of signal processing algorithms. The letter reports on the development of a bit-level 2-port systolic adaptor for wave digital filters (WDFs). The 2-port adaptor can be used for the realisation of WDFs based on the cascade of unit elements and lattice analogue filters. The VLSI design of the adaptor is accomplished using the SOLO 1400 design tool.

A micro signal processing module

A small, high-speed programmable digital signal processing module utilizing bit slice microprocessor techniques is described. The processor is designed to provide low-cost, modular implementations of digital signal processing tasks, such as fast Fourier transforms, data compression, digital filtering, etc. The module demonstrates the use of recent LSI technology in a small compact design for both single and multiple processor implementation of signal processing algorithms.