Implementations Of Cryptographic Algorithms Research Articles

Efficiently Detecting Masking Flaws in Software Implementations

Software implementations of cryptographic algorithms often use masking schemes as a countermeasure against side channel attacks. A number of recent results show clearly the challenge of implementing masking schemes in such a way, that (unforeseen) micro-architectural effects do not cause masking flaws that undermine the intended security goal of an implementation. So far, utilising a higher-order version of the non-specific (fixed-vs-random) input test of the Test Vector Leakage Assessment (TVLA) framework has been the best option to identify such flaws. The drawbacks of this method are both its significant computation cost, as well as its inability to pinpoint which interaction of masking shares leads to the flaw. In this paper we propose a novel version, the fixed-vs-random shares test, to tackle both drawbacks. We explain our method and show its application to three case studies, where each time it outperforms its conventional TVLA counterpart. The drawback of our method is that it requires control over the shares, which, we argue, is practically feasible in the context of in-house evaluation and testing for software implementations.

IMPLEMENTASI ALGORITMA BLOWFISH PADA SISTEM MANAJEMEN SURAT DENGAN PENDEKATAN RATIONAL UNIFIED PROCESS YANG RAMAH LINGKUNGAN

In many organizations, including the Institut Teknologi Perusahaan Listrik Negara (ITPLN), letter management and organization is very important. This process is often resource-intensive and time-consuming. With the advancement of information technology, a secure digital system can help optimize letter management. The implementation of Blowfish cryptographic algorithm for encryption of important data on letter stored in a digital-based letter management system is the subject of this research. This method lowers the potential for eavesdropping and data theft. In the development process of this system, the Rational Unified Process (RUP) methodology takes the principle of green computing, which helps improve the efficiency of environmental destruction. The system adopts a paperless office paradigm, addresses the issue of operational inefficiencies, and safeguards sensitive data. The Blowfish algorithm prevents irresponsible people from compromising the database. This research produces a secure letter management information system using blowfish algorithm and developed using RUP that is environmentally friendly in contribution to the efficiency of environmental destruction caused by software development. Keywords: Blowfish Algorithm, Rational Unified Process, Data Security, Letter Management, Eco-Friendly Software

Breaking Ground: A New Area Record for Low-Latency First-Order Masked SHA-3

SHA-3, the latest hash standard from NIST, is utilized by numerous cryptographic algorithms to handle sensitive information. Consequently, SHA-3 has become a prime target for side-channel attacks, with numerous studies demonstrating successful breaches in unprotected implementations. Masking, a countermeasure capable of providing theoretical security, has been explored in various studies to protect SHA-3. However, masking for hardware implementations may significantly increase area costs and introduce additional delays, substantially impacting the speed and area of higher-level algorithms. In particular, current low-latency first-order masked SHA-3 hardware implementations require more than four times the area of unprotected implementations. To date, the specific structure of SHA-3 has not been thoroughly analyzed for exploitation in the context of masking design, leading to difficulties in minimizing the associated area costs using existing methods. We bridge this gap by conducting detailed leakage path and data dependency analyses on two-share masked SHA-3 implementations. Based on these analyses, we propose a compact and low-latency first-order SHA-3 masked hardware implementation, requiring only three times the area of unprotected implementations and almost no fresh random number demand. We also present a complete theoretical security proof for the proposed implementation in the glitch+register-transition-robust probing model. Additionally, we conduct leakage detection experiments using PROLEAD, TVLA and VerMI to complement the theoretical evidence. Compared to state-of-theart designs, our implementation achieves a 28% reduction in area consumption. Our design can be integrated into first-order implementations of higher-level cryptographic algorithms, contributing to a reduction in overall area costs.

Closing the Gap: Leakage Contracts for Processors with Transitions and Glitches

Security verification of masked software implementations of cryptographic algorithms must account for microarchitectural side-effects of CPUs. Leakage contracts were proposed to provide a formal separation between hardware and software verification, ensuring interoperability and end-to-end security for independently verified components. However, previously proposed leakage contracts did not consider a class of ephemeral hardware effects called glitches, which leaves a considerable gap between security models and the capabilities of real-world attackers. We address this issue by extending the model for leakage contracts to account for glitches and transitions. We further present the first end-to-end verification tool for transient leakage contracts. Our hardware and software verification rely on the same contract as a single source of truth, facilitating fully machine-checked verification from the hardware gate level to the software. By allowing contracts to be written in the C programming language we make power contracts more accessible and intuitive for system-level engineers. To showcase the efficacy of our approach, we apply it to the RISC-V Ibex core. We show that it is possible to write a power contract for Ibex without any modifications to the hardware design. Using this contract, we prove end-to-end security between masked software and gate-level hardware.

Novel optimized implementations for the Piccolo cipher based on field‐programmable gate arrays

AbstractIn the era of the highly pervasive Internet of Things (IoT), the optimized implementation of lightweight cryptographic algorithms for protecting data security has extensively received attention, for instance, the Piccolo cipher. Piccolo is an ultra‐lightweight block cipher designed for extremely resource‐constrained devices. Currently, many optimized implementations of Piccolo have been proposed; however, these implementations are heavily rely on optimizing different architectures. Actually, these implementation schemes have all neglected the optimization of the core components. How to achieve the new optimized implementation of the Piccolo cipher (via both the architectures and the core components) appears to be an interesting problem. In this article, new circuit structures for components (key schedules and round functions) of the Piccolo are first proposed using fewer logic gates. Based on these circuit structures, three architectures (iterative, integrated iterative, and scalar) are proposed to maximize implementation performances. To demonstrate their effectiveness and practicality, these architectures are simulated and synthesized on different field‐programmable gate arrays (FPGA) devices. Compared with the existing architectures of Piccolo, the results indicate that the iterative architectures and the integrated iterative architecture provide a better trade‐off between area and throughput, and the scalar architectures provide the highest throughput. Especially for Piccolo‐128, the area of its iterative architecture is 30 look‐up tables (LUTs) and 22 slices less than the best known implementation; the throughput and efficiency are 68.56% higher and twice higher than the best known implementation, respectively. Compared with other block ciphers, the efficiency and area‐delay product of the Piccolo‐128 iterative architecture outperform PRESENT, GIFT, SIMON, Midori, SIMON, and SIMECK. Compared with the best results, its encryption efficiency has increased by 31.53%, and the area‐delay product has decreased by 44.63%.

CLFuzz: Vulnerability Detection of Cryptographic Algorithm Implementation via Semantic-aware Fuzzing

Cryptography is a core component of many security applications, and flaws hidden in its implementation will affect the functional integrity or, more severely, pose threats to data security. Hence, guaranteeing the correctness of the implementation is important. However, the semantic characteristics (e.g., diverse input data and complex functional transformation) challenge those traditional program validation techniques (e.g., static analysis and dynamic fuzzing). In this article, we propose CLFuzz, a semantic-aware fuzzer for the vulnerability detection of cryptographic algorithm implementation. CLFuzz first extracts the semantic information of targeted algorithms including their cryptographic-specific constraints and function signatures. Based on them, CLFuzz generates high-quality input data adaptively to trigger error-prone situations efficiently. Furthermore, CLFuzz applies innovative logical cross-check that strengthens the logical bug detection ability. We evaluate CLFuzz on the widely used implementations of 54 cryptographic algorithms. It outperforms state-of-the-art cryptographic fuzzing tools. For example, compared with Cryptofuzz, it achieves a coverage speedup of 3.4× and increases the final coverage by 14.4%. Furthermore, CLFuzz has detected 12 previously unknown implementation bugs in 8 cryptographic algorithms (e.g., CMAC in OpenSSL and Message Digest in SymCrypt), most of which are security-critical and have been successfully collected in the national vulnerability database (7 in NVD/CNVD) and is awarded by the Microsoft bounty program (2 for $1,000).

RegKey: A Register-based Implementation of ECC Signature Algorithms Against One-shot Memory Disclosure

To ensure the security of cryptographic algorithm implementations, several cryptographic key protection schemes have been proposed to prevent various memory disclosure attacks. Among them, the register-based solutions do not rely on special hardware features and offer better applicability. However, due to the size limitation of register resources, the performance of register-based solutions is much worse than conventional cryptosystem implementations without security enhancements. This paper presents RegKey, an efficient register-based implementation of ECC (elliptic curve cryptography) signature algorithms. Different from other schemes that protect the whole cryptographic operations, RegKey only uses CPU registers to execute simple but critical operations, significantly reducing the usage of register resources and performance overheads. To achieve this goal, RegKey splits the ECC signing into two parts, (1) complex elliptic curve group operations on non-sensitive data in main memory as normal implementations, and (2) simple prime field operations on sensitive data inside CPU registers. RegKey guarantees the plaintext private key and random number used for signing only appear in registers to effectively resist one-shot memory disclosure attacks such as cold-boot attacks and warm-boot attacks, which are usually launched by physically accessing the victim machine to acquire partial or even entire memory data but only once. Compared with existing cryptographic key protection schemes, the performance of RegKey is greatly improved. Regkey is applicable to different platforms because it does not rely on special CPU hardware features. Since RegKey focuses on one-shot memory disclosure instead of persistent software-based attacks, it works as a choice suitable for embedded devices or offline machines where physical attacks are the main threat.

Hash Function Design Based on Hybrid Five-Neighborhood Cellular Automata and Sponge Functions

In today’s world of pervasive computing, all the devices have become smart. The need for securing these devices becomes a need of the hour. The traditional cryptographic algorithms will not be ideal for small devices, and this opens a new area of cryptography named lightweight cryptography, which focuses on the implementation of cryptographic algorithms in resource-constrained devices without compromise in security. Cryptographic hash functions enable detection of message tampering by adversaries. This paper proposes a lightweight hash function that makes use of sponge functions and higher radii hybrid cellular automata (CAs). The proposed hash function shows good cryptographic properties as well as collision resistance and serves as an ideal hash function for lightweight applications.

A Comparative Study of Post-Quantum Cryptographic Algorithm Implementations for Secure and Efficient Energy Systems Monitoring

The Internet of Things (IoT) has assumed a pivotal role in the advancement of communication technology and in our daily lives. However, an IoT system such as a smart grid with poorly designed topology and weak security protocols might be vulnerable to cybercrimes. Exploits may arise from sensor data interception en route to the intended consumer within an IoT system. The increasing integration of electronic devices interconnected via the internet has galvanized the acceptance of this technology. Nonetheless, as the number of users of this technology surges, there must be an aligned concern to ensure that security measures are diligently enforced within IoT communication systems, such as in smart homes, smart cities, smart factories, smart hospitals, and smart grids. This research addresses security lacunae in the topology and configuration of IoT energy monitoring systems using post-quantum cryptographic techniques. We propose tailored implementations of the Rivest–Shamir–Adleman (RSA), N-th degree Truncated Polynomial Ring Units (NTRU), and a suite of cryptographic primitives based on Module Learning With Rounding (Saber) as post-quantum cryptographic candidate algorithms for IoT devices. These aim to secure publisher–subscriber end-to-end communication in energy system monitoring. Additionally, we offer a comparative analysis of these tailored implementations on low-resource devices, such as the Raspberry Pi, during data transmission using the Message Queuing Telemetry Transport (MQTT) protocol. Results indicate that the customized implementation of NTRU outperforms both SABER and RSA in terms of CPU and memory usage, while Light SABER emerges as the front-runner when considering encryption and decryption delays.

A high‐speed and low‐latency hardware implementation of RC4 cryptographic algorithm

AbstractIn this letter, a high‐speed and low‐latency Ron Rivest‐4 (RC4) encryption algorithm is designed based on SMIC 14 nm process. Since the key issue of limiting the throughput of RC4 encryption algorithm is the swapping operation of S‐box, this proposed design is capable of achieving four swapping operations of S‐box within a clock cycle by utilizing fully combinational logic designs and advanced computations. All 256 swapping operations of key scheduling algorithm (KSA) can be done in 64 clock cycles. Moreover, the novel design greatly improves the encryption efficiency of RC4 since each clock cycle offers 4 bytes of key stream. The whole area can be further optimized by reusing the existing modules, and a lightweight countermeasure is embedded into the RC4 design to break the correlation between the processed data and power dissipation against differential power analysis (DPA) attacks. Finally, the whole design is assessed by the SMIC 14 nm process design kits (PDK). The corresponding clock frequency, throughput, area, and latency, respectively, are achieved as 1 GHz, 32 Gbps, 51,596 m2, and 74 clock cycles.

FFCSA - Finite Field Constructions, Search, and Algorithms

In this work we present the new GAP package FFCSA - Finite Field Constructions, Search, and Algorithms. It was designed to enable Design Space Exploration for hardware implementations of cryptographic algorithms defined over finite fields. FFCSA constructions and searches are used to produce the design space, and FFCSA algorithms, parameterized for the current candidate field, are used to generate expressions needed for implementation in hardware.

Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA

The security of Internet of Things (IoTs) devices in recent years has created interest in developing implementations of lightweight cryptographic algorithms for such systems. Additionally, open-source hardware and field-programable gate arrays (FPGAs) are gaining traction via newly developed tools, frameworks, and HDLs. This enables new methods of creating hardware and systems faster, more simply, and more efficiently. In this paper, the implementation of a system-on-chip (SoC) based on a 32-bit RISC-V processor with lightweight cryptographic accelerator cores in FPGA and an open-source integrating framework is presented. The system consists of a 32-bit VexRiscv processor, written in SpinalHDL, and lightweight cryptographic accelerator cores for the PRINCE block cipher, the PRESENT-80 block cipher, the ChaCha stream cipher, and the SHA3-512 hash function, written in Verilog HDL and optimized for low latency with fewer clock cycles. The primary aim of this work was to develop a customized SoC platform with a register-controlled bus suitable for integrating lightweight cryptographic cores to become compact embedded systems that require encryption functionalities. Additionally, custom firmware was developed to verify the functionality of the SoC with all integrated accelerator cores, and to evaluate the speed of cryptographic processing. The proposed system was successfully implemented in a Xilinx Nexys4 DDR FPGA development board. The resources of the system in the FPGA were low with 11,830 LUTs and 9552 FFs. The proposed system can be applicable to enhancing the security of Internet of Things systems.

Revisiting Multiple Ring Oscillator-Based True Random Generators to Achieve Compact Implementations on FPGAs for Cryptographic Applications

The generation of random numbers is crucial for practical implementations of cryptographic algorithms. In this sense, hardware security modules (HSMs) include true random number generators (TRNGs) implemented in hardware to achieve good random number generation. In the case of cryptographic algorithms implemented on FPGAs, the hardware implementation of RNGs is limited to the programmable cells in the device. Among the different proposals to obtain sources of entropy and process them to implement TRNGs, those based in ring oscillators (ROs), operating in parallel and combined with XOR gates, present good statistical properties at the cost of high area requirements. In this paper, these TRNGs are revisited, showing a method for area optimization independently of the FPGA technology used. Experimental results show that three ring oscillators requiring only three LUTs are enough to build a TRNG on Artix 7 devices from Xilinx with a throughput of 33.3 Kbps, which passes NIST tests. A throughput of 50 Kbps can be achieved with four ring oscillators, also requiring three LUTs in Artix 7 devices, while 100 Kbps can be achieved using an structure with four ring oscillators requiring seven LUTs.

On some relations of SCA-related properties of S-box under the Hamming weight leakage mode

Abstract— Physical implementations of cryptographic algorithms are vulnerable to so-called side-channel attacks, in which sensitive information can be recovered through the analysis of the leakages produced by the operating device. In the particular case of block ciphers, substitution boxes are often the target of such attacks, as they are the main nonlinear component of the cipher. Literature survey contains some definitions of theoretical properties to measure the resistance provided by substitution boxes with respect to the imminent threat of side-channel attacks. The fundamental questions we board in this paper are: are all these properties related? And if so, what can we tell of their relation? We pretend to bring some clarification to this subject using some well-known side-channel related properties of S-box.

Word-Based Processor Structure for Montgomery Modular Multiplier Suitable for Compact IoT Edge Devices

The Internet of Things (IoT) is an emerging technology that forms a huge network of different objects and intelligent devices. IoT Security is becoming more important due to the exchange of sensitive sensor data and the potential for incorporating the virtual and real worlds. IoT edge devices create serious security threats to network systems. Due to their limited resources, it is challenging to implement cryptographic protocols on these devices to secure them. To address this problem, we should perform compact implementation of cryptographic algorithms on these devices. At the heart of most cryptographic algorithms is the modular multiplication operation. Therefore, efficient implementation of this operation will have a great impact on the implementation of the whole cryptographic protocol. In this paper, we will focus on the resource and energy efficient hardware implementation of the adopted Montgomery modular multiplication algorithm over GF(2m). The main building block of the proposed word-based processor structure is a processor array that has a modular structure with local connectivity between its processing elements. The ability to manage the saving amounts of area, delay, and consumed energy is the main benefit of the suggested hardware structure. We used ASIC technology to implement the suggested word-based processor structure. The final results show an average reduction in the area of 86.3% when compared with the competitive word-based multiplier structures. Additionally, the recommended design achieves significant average savings in area-time product, power, and consumed energy of 53.7%, 83.2%, and 72.6%, receptively, over the competitive ones. The obtained results show that the provided processor structure is best suited for application in compact IoT edge devices with limited resources.

Protecting integrated circuits against side-channel and fault attacks with dynamic encoding

With the Internet of Things, an increasing amount of sensitive data have to be communicated and hence encrypted. Low-cost hardware attacks such as fault analysis or side-channel analysis threaten the implementation of cryptographic algorithms. Many countermeasures have been proposed against either of these attacks, however, only a few countermeasures protect efficiently an implementation against both attacks. These joint countermeasures usually have a prohibitive area and power overhead, and require up to thousands of bits of fresh randomness at each encryption. Therefore, they may not be suited to protect lightweight algorithms in resource-constrained devices. In this paper, we propose a new joint countermeasure against both attacks, called dynamic encoding. It has a smaller power and area overhead than existing joint countermeasures and requires at most 8 random bits at each encryption. It is particularly adapted to protect sequential logic and lightweight algorithms based on shift registers, and it can be extended to protect combinational logic as well. It consists in a power balancing at algorithmic level and provides an inherent fault detection. Simulations with several levels of noise indicate that dynamic encoding provides an efficient protection against side-channel analysis with up to 100,000 traces.

Secure efficient communication in routing protocol in MANETs using ECC-EA3ACKa

Mobile Ad Hoc Networks (MANETs) are dynamic, self-organizing networks that lack a fixed infrastructure, making them highly vulnerable to various security threats. One of the critical aspects in MANETs is the establishment of efficient and secure communication among mobile nodes. Routing protocols play a pivotal role in ensuring reliable data transmission in such environments. This paper presents a comprehensive overview of the challenges and solutions related to achieving secure and efficient communication within MANET routing protocols. The main objective of this paper is to define the path for security and to further improve throughput, routing overhead, end-to-end delay, packet delivery ratio, and at the same time to create an energy-enhanced way with excellent security. Implementation of cryptographic algorithms for the information is done in such a way that it is impossible for attackers to compromise the resources of information sent over the web. This paper proposes a new intrusion detection system called Enhanced Adaptive 3 Acknowledgement (ECC-EA3ACK), using EA3ACK with Elliptical Curve Cryptography (ECC) specially designed for MANETs. In this ECC, there is a two-key encryption technique based on elliptic curve theory that can be used to create faster, smaller, more energy-efficient cryptography. The above-developed on-demand routing protocol achieves better results than the existing model through one of the leading simulators called Network Simulator (NS2), which is used to implement and test the proposed system. The proposed cryptography provides secured transmission, reduces routing overhead, improves packet delivery ratio, throughput, and minimizes delay due to increased remaining energy and improved security.

ВПЛИВАТАК ЗА ПОБІЧНИМИ КАНАЛАМИ НА ІНФОРМАЦІЙНУ БЕЗПЕКУ

The main structural elements of security mechanisms based on cryptography are cryptographic primitives, namely cryptographic algorithms -symmetric ciphers, public key ciphers and hash functions, which are used to implement the necessary functions of the security mechanism. In order for the cryptographic system to ensure information security, it is necessary that the secret keys used in the cryptographic algorithms for security implementation remain secret (not revealed) under any circumstances. However, in practice, the implementation and operation of cryptographic security mechanisms is far from the perfection of an ideal "black box". That is why side channel attacks are a serious threat to the security of cryptographic modules and, as a result, to the information security of computing and communication systems. Therefore, when implementing protection mechanisms, all possibilities of such attacks should be evaluated and all aspects of their application should be taken into account.The analysis of scientific works in the field of protection of cryptographic systems against attacks by side channels proved that these issues are not given enough attention today.The purpose of the article is the study of attacks through side channels on the implementation of crypto-protection mechanisms, the analysis of the features of their implementation, and an overview of the mechanisms for ensuring information security during the destructive effects of these attacks.The paper considers one of the practical directions of cryptanalysis -attacks through side channels on the implementation of crypto-protection mechanisms. The differences between theoretical cryptanalysis and side-channel attacks are studied. The possibilities of side-channel attacks and the specifics of failure injection attacks are analyzed. The features of ensuring information security during the implementation of cryptographic algorithms for protection against side channel attacks are considered. The need to take into account the threat of these attacks when ensuring the information security of computer and communication systems is proven

An extended analytical framework for heterogeneous implementations of light cryptographic algorithms

The increased need for data, combined with the emergence of powerful Internet of Things (IoT) devices, has resulted in major security concerns. The decision-making related to choosing an adequate cryptographic algorithm to use is, indeed, an example concern that affects the performance of an implementation. Lightweight or tiny ciphers are considered to be the go-to algorithms when talking about embedded systems and IoT devices. Such ciphers, when properly integrated, are expected to have a minimal effect on the overall device utilization and thus provide effective performance. In this paper, we propose a unified analytical framework for lightweight ciphers as implemented within heterogeneous computing environments. This framework considers a carefully identified set of metrics that can adequately enable the capturing, ranking, and classifying the attained performance. To that end, a designer can make effective evaluations and exact adjustments to an implementation. This framework uses three decision-making approaches, namely the Technique for Order of Preference by Similarity to Ideal Solution (TOPSIS), Preference Ranking Organization Method for Enrichment Evaluation (PROMETHEE) II, and Fuzzy TOPSIS. Such approaches take into account both hardware and software metrics when deciding on a suitable cryptographic algorithm to adopt. Validation entails a thorough examination and evaluation of several performance classification schemes. The results confirm that the framework is both valid and effective.

Equivalent Keys: Side-Channel Countermeasure for Post-Quantum Multivariate Quadratic Signatures

Algorithms based on the hardness of solving multivariate quadratic equations present promising candidates for post-quantum digital signatures. Contemporary threats to implementations of cryptographic algorithms, especially in embedded systems, include side-channel analysis, where attacks such as differential power analysis allow for the extraction of secret keys from the device’s power consumption or its electromagnetic emission. To prevent these attacks, various countermeasures must be implemented. In this paper, we propose a novel side-channel countermeasure for multivariate quadratic digital signatures through the concept of equivalent private keys. We propose a random equivalent key to be generated prior to every signing, thus randomizing the computation and mitigating side-channel attacks. We demonstrate our approach on the Rainbow digital signature, but since an unbalanced oil and vinegar is its special case, our work is applicable to other multivariate quadratic signature schemes as well. We analyze the proposed countermeasure regarding its properties such as the number of different equivalent keys or the amount of required fresh randomness, and we propose an efficient way to implement the countermeasure. We evaluate its performance regarding side-channel leakage and time/memory requirements. Using test vector leakage assessment, we were not able to detect any statistically significant leakage from our protected implementation.