Implementation Of S-box Research Articles

Design and implementation of dynamic s-boxes based on non-degenerate discrete chaotic systems

In recent years, digital chaotic systems have received considerable attention in the field of secure communications. However, during the digitalization of the system, the original properties of the chaotic system may change, resulting in the degradation of the dynamics. To address this problem, this paper designs a novel simplicial non-degenerate discrete chaotic system based on the inverse hyperbolic tangent function, and selects a three-dimensional discrete system as the object of analysis. Through the research conducted, it is found that the chaotic system exhibits high Lyapunov exponents under certain conditions. Furthermore, the excellent randomness of the system has been further validated by NIST SP800–22 tests. At the same time, this paper also proposes a dynamic S-box construction method based on the chaotic sequence generated from the three-dimensional chaotic mapping. By performing a series of basic operations and permutation treatment, many dynamic S-boxes can be generated. This paper comprehensively analyses the performance of S-boxes from two perspectives: single S-boxes and multiple S-boxes. The analysis covers issues such as bijective property, nonlinearity, strict avalanche criterion, differential approximation probability and bit independence criteria. The results of the performance analysis show that the dynamically generated S-boxes have excellent cryptographic properties, making them suitable for the design and application of cryptographic algorithms.

FPGA Implementation of 256-Bit Key AES Algorithm

Abstract: The most popular network security technique for secure data transmission between two end users, particularly over a public network, is the AES algorithm, also known as the Rijndael algorithm. It may be found in all kinds of wired and wireless digital communication networks AES, a network security technique, uses 256 bits on an FPGA. An authorized cryptographic technique that can be used to secure electronic data is the Advanced Encryption Standard technique (AES), which is specified by the National Institute of Standards and Technology. Because they provide faster and more flexible solutions, reprogrammable devices like Field Programmable Arrays (FPGA) are a very appealing alternative for hardware implementation of the encryption algorithm AES. The effective FPGA implementation of advanced encryption standards (AES) is proposed in this research. The encryption code is written in the Verilog programming language. The AES Rijndael algorithm performs better than any other when implemented on FPGA. Other works are covered by this implementation to demonstrate its effectiveness. The block and key sizes in the design are 256, and an iterative looping technique is used. Bits, S-box implementation using lookup tables. This results in a low-complexity design that can readily achieve high throughput and low latency

Efficient implementations of CRAFT cipher for Internet of Things

The rapid growth of the Internet of Things (IoT) highlights the importance of lightweight cryptography in maintaining security. However, enhancing performance while ensuring the same level of security remains a significant challenge. This paper presents two innovative architectures for the CRAFT lightweight block cipher, aiming to enhance performance without compromising security. The novel Serial and Unrolled architectures are introduced to achieve low area usage and high throughput, respectively. Specifically, the Serial architecture reduces the datapath from 64-bit to 4-bit, significantly decreasing the area. The Unrolled architecture, on the other hand, minimizes latency from 32 to 16. Additionally, Boolean satisfiability (SAT) solvers are employed to identify a lower-cost area implementation of the S-Box. The proposed designs underwent evaluation on three distinct FPGA platforms: Artix-7, Kintex-7, and Spartan-7. The results show that the low area design reduces area usage by 10.16% compared to the previous design. Additionally, the S-Box implementation achieves a significant area reduction of 28.9%. On the other hand, the unrolled design enhances the maximum throughput by 40.53% compared to the previous design. Therefore, the proposed designs could offer enhanced performance while maintaining security for IoT devices.

FPGA-friendly compact and efficient AES-like 8 × 8 S-box

One of the main layers in the Advanced Encryption Standard (AES) is the substitution layer, where an 8 × 8 S-Box is used 16 times. The substitution layer provides confusion and makes the algorithm resistant to cryptanalysis techniques. Therefore, the security of the algorithm is also highly dependent on this layer. However, the cost of implementing 8 × 8 S-Box on FPGA platforms is considerably higher than other layers of the algorithm. Since S-Boxes are repeatedly used in the algorithm, the cost of the algorithm highly comes from the substitution layer. In 2005, Canright used different extension fields to represent AES S-Box to get FPGA-friendly compact designs. The best optimization proposed by Canright reduced the gate-area of the AES S-Box implementation by 20%.In this study, we use the same optimization methods that Canright used to optimize AES S-Box on hardware platforms. Our purpose is not to optimize AES S-Box; we aim to create another 8 × 8 S-Box which is strong and compact enough for FPGA platforms. We create an 8 × 8 S-Box using the inverse field operation as in the case of AES S-Box. We use another irreducible polynomial to represent the finite field and get an FPGA-friendly compact and efficient 8 × 8 S-Box. The finite field we propose provides the same level of security against cryptanalysis techniques with a 3.125% less gate-area on Virtex-7 and Artix-7 FPGAs compared to Canright’s results. Moreover, our proposed S-Box requires 11.76% less gate on Virtex-4 FPGAs. These gate-area improvements are beneficial for resource-constraint IoT devices and allow more copies of the S-Box for algorithm parallelism. Therefore, we claim that our proposed S-Box is more compact and efficient than AES S-Box. Cryptographers who need an 8 × 8 S-Box can use our proposed S-Box in their designs instead of AES S-Box with the same level of security but better efficiency.

A High Efficiency Hardware Implementation of S-Boxes Based on Composite Field for Advanced Encryption Standard

A High Efficiency Hardware Implementation of S-Boxes Based on Composite Field for Advanced Encryption Standard

Improving the Performance of CPA Attacks for Ciphers Using Parallel Implementation of S-Boxes

Since their introduction in early 2000, CPA (correlation power analysis), as a cryptographic tool, has been widely used in the cryptanalysis of cryptographic algorithms (being applicable to both symmetric key ciphers as well as to public key encryption schemes). An application of the classical CPA method, along with its variants, to cryptographic algorithms that use parallel implementation of its substitution boxes (S-boxes) commonly requires more power traces to extract the secret key compared to the case when serial implementation of S-boxes is employed. To reduce the amount of power traces in this scenario, we propose a modification of the standard CPA approaches and demonstrate practically that our method performs better than the existing ones in this respect. To verify the efficiency of our improved CPA method, we apply it to the public databases of DPA Contest V2. In particular, the experimental results show that only 495 power traces are required to recover the secret key of AES. We also compare the performance of our attack to the relevant methods whose parameters are available at DPA Contest V2. The results show that compared to the best nonprofiling side-channel attack (SCA) attack, our method reduces the number of power traces required to recover the secret key by 6,566. Also, our new method performs almost similarly as the best profiling SCA attack of Benoit Gerard (in terms of the required number of power traces), thus reducing the gap in the performance of profiling and nonprofiling SCA attacks.

Description, Implementation and Performance/Security Analysis of ASCON128

The aim of the report is to introduce detailed description of the functioning of and to provide an efficient implementation (using bit-sliced implementation of S-Box) in C of encryption, decryption and authentication of the lightweight authenticated encryption algorithm ASCON 128 (sponge based SPN network based on Keccak like operations) as per the v 1.2 submitted to NIST. This is achieved using a sponge construction by setting up initialization state and performing 12 rounds of permutations, XORing consecutively the plaintext blocks (encryption) or ciphertext blocks (decryption) with first 64 bits of the state (after 6 rounds of sponge permutations) and after all consecutive operations on ciphertext/plaintext blocks, XORing the last 128 bits of the resultant state with the secret Key (after 12 rounds of final permutation operations) to produce/re-create the tag. Discussions on Key Features, Performance Analysis (comparison of ASCON 128 v/s AES 128 in GCM mode on our own PC), Performance Comparisons with other NIST lightweight cryptography contest finalists on ARM Cortex M3, and discussions on the Security Analysis (side channel attacks: fault injection and power analysis) of ASCON are included in this report.

Implementation of Pipelined S-BOX Using Field Programmable Gate Array

In this project, the Advanced Encryption Standard (AES) S-box implementation is covered in detail. An S-box is a table or function replacing input values with encrypted output values, enhancing cryptographic security. To introduce the idea of pipelining, the S-box is created using GF((2^4)^2) and the Composite Field Arithmetic (CFA) approach. Pipelining in substitution box involves processing input through stages, enhancing efficiency by overlapping operations, thereby improving throughput in cryptographic algorithms like AES. To create combinational logic, the proposed architecture uses affine mapping, Composite transformation, and Inverse Galois field arithmetic. This designed S-box model is checked for functionality and synthesized to check for resource utilization. The same design is checked for timing violations and tuned to a particular frequency. Power Analysis is performed to ensure the design will not exceed the limited power. Finally, the design is converted into a bit file to dump onto the Spartan 6 FPGA Board. This method of S-box design is better than the conventional S-box, which was based on LUT.

Low Area and Low Power Threshold Implementation Design Technique for AES S-Box

Threshold implementation (TI) is a promising countermeasure against side-channel attacks (SCA) in the presence of glitches. However, the hardware implementation of TI in S-box needs a large number of D flip-flops to synchronize intermediate signals, which results in a large silicon area and power consumption overhead. In this brief, we present the low area and low power TI design technique for advanced encryption standard (AES) S-box. In the proposed approach, instead of using D flip-flops, low-cost synchronization circuits such as customized tri-state XOR gates, tri-state buffers, and D latches are efficiently adopted with critical path replica (CPR) circuits. As a result, the proposed TI S-box implementation with 28nm CMOS process shows up to 33.7% area and 44.3% power savings. The security of the proposed TI AES S-box against side-channel attacks is also verified with test vector leakage assessment (TVLA) tests.

Hardware Implementation of High-Throughput S-Box in AES for Information Security

Hardware Implementation of High-Throughput S-Box in AES for Information Security

Searching the space of tower field implementations of the 𝔽<SUB align="right">2<SUP align="right">8</SUP> inverter - with applications to AES, Camellia and SM4

No AccessSearching the space of tower field implementations of the 𝔽28 inverter - with applications to AES, Camellia and SM4Zihao Wei, Siwei Sun, Lei Hu, Man Wei and René PeraltaZihao WeiState Key Laboratory of Information Security, Institute of Information Engineering, Chinese Academy of Sciences, Beijing 100093, China; School of Cyber Security, University of Chinese Academy of Sciences, Beijing 100049, China, Siwei SunState Key Laboratory of Information Security, Institute of Information Engineering, Chinese Academy of Sciences, Beijing 100093, China; School of Cyber Security, University of Chinese Academy of Sciences, Beijing 100049, China, Lei HuState Key Laboratory of Information Security, Institute of Information Engineering, Chinese Academy of Sciences, Beijing 100093, China; School of Cyber Security, University of Chinese Academy of Sciences, Beijing 100049, China, Man WeiState Key Laboratory of Information Security, Institute of Information Engineering, Chinese Academy of Sciences, Beijing 100093, China; School of Cyber Security, University of Chinese Academy of Sciences, Beijing 100049, China and René PeraltaComputer Security Division, NIST, 100 Bureau Drive, Stop 8930, Gaithersburg, MD 20899-8930, USAPublished Online:December 21, 2022pp 1-26https://doi.org/10.1504/IJICS.2023.127999PDF ToolsAdd to FavouritesDownload CitationsTrack Citations Share this article on social mediaShareShare onFacebookTwitterLinkedInReddit AboutAbstractThe tower field implementation of the 𝔽28 inverter is not only the key technique for compact implementations of the S-boxes of several internationally standardised block ciphers such as AES, Camellia, and SM4, but also the underlying structure many side-channel attack resistant AES implementations rely on. In this work, we conduct an exhaustive study of the tower field representations of the 𝔽28 inverter with normal bases by applying several state-of-the-art combinatorial logic minimisation techniques. As a result, we achieve improved implementations of the AES, Camellia and SM4 S-boxes in terms of area footprint. Surprisingly, we are still able to improve the currently known most compact implementation of the AES S-box from CHES 2018 by 5.5 GE, beating the record again. For Camellia and SM4, the improvements are even more significant. The Verilog codes of our implementations of the AES, Camellia and SM4 S-boxes are openly available.Keywordstower field, inverter, S-box, AES, Camellia, SM4 Next article FiguresReferencesRelatedDetails Volume 20Issue 1-22023 ISSN: 1744-1765eISSN: 1744-1773 HistoryPublished onlineDecember 21, 2022 Copyright © 2023 Inderscience Enterprises Ltd.Keywordstower fieldinverterS-boxAESCamelliaSM4Authors and AffiliationsZihao Wei1 Siwei Sun2 Lei Hu3 Man Wei4 René Peralta5 1. State Key Laboratory of Information Security, Institute of Information Engineering, Chinese Academy of Sciences, Beijing 100093, China; School of Cyber Security, University of Chinese Academy of Sciences, Beijing 100049, China2. State Key Laboratory of Information Security, Institute of Information Engineering, Chinese Academy of Sciences, Beijing 100093, China; School of Cyber Security, University of Chinese Academy of Sciences, Beijing 100049, China3. State Key Laboratory of Information Security, Institute of Information Engineering, Chinese Academy of Sciences, Beijing 100093, China; School of Cyber Security, University of Chinese Academy of Sciences, Beijing 100049, China4. State Key Laboratory of Information Security, Institute of Information Engineering, Chinese Academy of Sciences, Beijing 100093, China; School of Cyber Security, University of Chinese Academy of Sciences, Beijing 100049, China5. Computer Security Division, NIST, 100 Bureau Drive, Stop 8930, Gaithersburg, MD 20899-8930, USAPDF download

A highly efficient FPGA implementation of AES for high throughput IoT applications

With nearly 500 billion connected devices in 2025, information security will be the main concern of the researchers. It is the driving force in developing resource efficient cryptographic solutions. In this paper, we present a high throughput AES design with 32-bit data path that achieves the high efficiency via FPGA implementation. With the help of data path compression and effective utilization of FPGA architecture, the resource consumption is minimized. Galois field arithmetic is utilized for s-box implementation. Separate S-box for key generation has been employed to achieve higher throughput and low latency. The proposed design has been synthesized by PlanAhead software and implemented on different Xilinx FPGAs. It is compared with AES implementations. With a throughput of 2.34 Gbps and efficiency of 5.10 Mbps/slice, the design outperforms different lightweight ciphers. High throughput and low latency make it suitable for surveillance applications in IoT and smart grid.

Alternative Tower Field Construction for Quantum Implementation of the AES S-Box

Grover’s search algorithm allows a quantum adversary to find a <inline-formula><tex-math notation="LaTeX">$k$</tex-math></inline-formula> -bit secret key of a block cipher by making O( <inline-formula><tex-math notation="LaTeX">$2^{k/2}$</tex-math></inline-formula> ) block cipher queries. Resistance of a block cipher to such an attack is evaluated by quantum resources required to implement Grover’s oracle for the target cipher. The quantum resources are typically estimated by the <inline-formula><tex-math notation="LaTeX">$\textit {T}$</tex-math></inline-formula> -depth of its circuit implementation and the number of qubits used by the circuit (width). Since the AES S-box is the only component which requires <inline-formula><tex-math notation="LaTeX">$\textit {T}$</tex-math></inline-formula> -gates in a quantum implementation of AES, recent research has put its focus on efficient implementation of the AES S-box. However, any efficient implementation with low <inline-formula><tex-math notation="LaTeX">$\textit {T}$</tex-math></inline-formula> -depth will not be practical in the real world without considering qubit consumption of the implementation. In this work, we propose three methods of trade-off between time and space for the quantum implementation of the AES S-box. In particular, one of our methods turns out to use the smallest number of qubits among the existing methods, significantly reducing its <inline-formula><tex-math notation="LaTeX">$\textit {T}$</tex-math></inline-formula> -depth.

High-throughput block cipher implementations with SIMD

The development of new technologies has put forward higher requirements for the performance and security of block ciphers. To meet the needs of these situations, Bitslicing is one of the block cipher implementation techniques which can provide high efficiency and resistance to cache-timing attacks. The S-box is usually the most time-consuming component for Bitsliced implementations. In this paper, we present techniques to optimize the S-box implementation and derive the most compact representations available for Bitslicing. Then we show that the efficiency of linear layers can be further improved by introducing a state-of-the-art technique. As a result, our implementations have significant advantages over previous implementations. The throughputs of our AES and SM4 implementations achieve 27068Mbps and 30026Mbps on i5-11335G7, both exceeding the throughput of AES-NI on the same platform.

FPGA IMPLEMENTATION OF PRESENT ALGORITHM FOR IOT APPLICATION

IoT is a global network with dynamic capabilities that use standard communication protocols. Security is the process of securing data as they are transmitted and exchanged among objects which can reduce the limitations. Cryptography is an important algorithm means in security that can be defined as converting plaintext into ciphertext.The algorithm of cryptography provides a high- level security but does not concern itself in hardware requirements like power consumption, computation cost, and memory overhead. To solve these challenges, special algorithms are designed and called light Weight Cryptography to be suitable for resource constrained devices. The goal of light Weight Cryptography is to reduce the overall implementation cost of traditional encryption, through several aspects such as area, throughput, latency, and power and energy consumption. Recently, several algorithms have been proposed for LWC. Comparing with different circumstances, we observed that PRESENT has much competence and many advantages. Several basic attacks PRESENT but all know attacks are ineffective. Given the importance of IoT security in this project, we are focusing on improving the S-Box implementation for essential measures such as power consumption and performance using Xilinx tool and spartan 7 and Artix 7 device. Software Tools:  Xilinx Vivado 2020.2  Quartus Prime and Modelsim Key Words:Cryptography, Lightweight Cryptography, SBOX, PBOX, Key Rounding, PRESENT Algorithm

Implementation of an 8-bit bit-slice AES S-box with rapid single flux quantum circuits

Rapid single flux quantum (RSFQ) circuits are a kind of superconducting digital circuits, having properties of a natural gate-level pipelining synchronous sequential circuit, which demonstrates high energy efficiency and high throughput advantage. We find that the high-throughput and high-speed performance of RSFQ circuits can take the advantage of a hardware implementation of the encryption algorithm, whereas these are rarely applied to this field. Among the available encryption algorithms, the advanced encryption standard (AES) algorithm is an advanced encryption standard algorithm. It is currently the most widely used symmetric cryptography algorithm. In this work, we aim to demonstrate the SubByte operation of an AES-128 algorithm using RSFQ circuits based on the SIMIT Nb03 process. We design an AES S-box circuit in the RSFQ logic, and compare its operational frequency, power dissipation, and throughput with those of the CMOS-based circuit post-simulated in the same structure. The complete RSFQ S-box circuit costs a total of 42237 Josephson junctions with nearly 130 Gbps throughput under the maximum simulated frequency of 16.28 GHz. Our analysis shows that the frequency and throughput of the RSFQ-based S-box are about four times higher than those of the CMOS-based S-box. Further, we design and fabricate a few typical modules of the S-box. Subsequent measurements demonstrate the correct functioning of the modules in both low and high frequencies up to 28.8 GHz.

Low-power AES S-box design using dual-basis tower field extension method for cyber security applications

In cryptography, one among several investigated areas is the implementation of AES S-boxes. In this paper, a substitution-box is designed which follows combined data path using dual-basis tower field extension with Golod–Shafarevich theorem fed in immune genetic algorithm for optimization purpose for each and every block. The role of enhanced immune genetic algorithm is as follows: at first, chaotic system generates S-boxes population, these S-boxes which perform excellently are then optimized by a sequence of operators such as extraction of anti-agent and immune selection. Few criteria of S-boxes such as differential uniformity, nonlinear degree, and strict avalanche effect are analyzed. The obtained results are analyzed with CMOS 35 nm and 15 nm technologies to measure the performance of the proposed designs and was observed that the proposed one outperforms in power and area. The optimized S-box can be effectively applied for securing information. The proposed Golod–Shafarevich feeder Immune Genetic Algorithm S-box (GSIGA-Sbox) is compared with two baseline methods such as Reversed Genetic Algorithm S-box (RGA-Sbox) and Discrete Space Chaotic S-box (DSC-Sbox). As a result the proposed GSIGA-Sbox achieves encryption speed of 61 MHZ, decryption speed of 55 MHZ with 24% of power consumption for 35 nm CMOS technology and 57 MHZ encryption speed, 51 MHZ decryption speed with 28% of power consumption for 15 nm CMOS technology.

Revealing the Weakness of Addition Chain Based Masked SBox Implementations

Addition chain is a well-known approach for implementing higher-order masked SBoxes. However, this approach induces more computations of intermediate monomials over F2n, which in turn leak more information related to the sensitive variables and may decrease its side-channel resistance consequently. In this paper, we introduce a new notion named polygon degree to measure the resistance of monomial computations. With the help of this notion, we select several typical addition chain implementations with the strongest or the weakest resistance. In practical experiments based on an ARM Cortex-M4 architecture, we collect power and electromagnetic traces in consideration of different noise levels. The results show that the resistance of the weakest masked SBox implementation is close to that of an unprotected implementation, while the strongest one can also be broken with fewer than 1,500 traces due to extra leakages. Moreover, we study the resistance of addition chain implementations against profiled attacks. We find that some monomials with smaller output size leak more information than the SBox output. The work by Duc et al. at JOC 2019 showed that for a balanced function, the smaller the output size is, the less information is leaked. Thus, our attacks demonstrate that this property of balanced functions does not apply to unbalanced functions.

On Hardware Implementation of Balanced S-boxes

An S-box is a non-linear transformation that takes n bits as input and returns m bits. This transformation is most easily represented as a nm lookup table. Most often, only balanced S-boxes are used in cryptography. This means that the number of input bits is equal to the number of output bits. The S-box is an important part of most symmetric ciphers. The selection of the correct substitution makes the link between the key and the ciphertext more complex (non-linear), which makes it much more difficult to hack. This paper deals with a hardware implementation of S-boxes. This implementation can be realized by using logical conjunction, disjunction, negation and delay blocks. The main indicator of productivity of such implementations is a circuit depth, namely the maximum length of a simple way of the circuit and a circuit complexity, namely the quantity of logic elements (negation elements are not taken into account). The article considers the standard synthesis methods (based on DNF, Shannon, Lupanov), proposes a new algorithm to minimize the complexity of an arbitrary Boolean functions system and a way to reduce the complexity of the circuit obtained after simplification by the ESPRESSO algorithm of DNF of the function related to the output of the S-box. To compare the efficiency of the methods, the C++ program was created that generates a circuit in the Verilog language. The estimates of depth and complexity are obtained for the schemes produced as a result of the programs operation. The article ends with a comparison of the efficiency of S-box schemes of known cryptographic standards obtained as the output of the program (with each other and with the result of the Logic Friday program).

RETRACTED: HPAC-sbox- a novel implementation of predictive learning classifier and adaptive chaotic s-box for counterfeiting sidechannel attacks in an IOT networks

ABSTRACT Today, embedded systems are augmented with the Internet of things and more with the artificial intelligence to make world even connected with aliens. With an IoT networks are getting its insight since it deals with large number of data information, security has considered to be more important and needs to be a diagnosis for every minute. To enhance the security in the network, a mathematically secure algorithms were formulated and runs on the cryptographic embedded chips to counterfeit the risks which are caused by the different attacks such as side channel attacks (SCA) on the networks. Even though many cryptographic encryption algorithms such as AES, DES, RC4 algorithms were gaining its importance, fixed encryption keys, non-intelligent detection of attacks, cognitive countermeasures are some of the real-time challenges in an existing system of encryption. Following the limitations of existing systems, this research article focuses on design of new AES with HPAC-SBOX (Hybrid Prediction and Adaptive Chaos) which integrates powerful predictive learning algorithms and adaptive chaotic logistic S-Box. The following contributions of this research articles are: a) Preparation of Data Sets from the Power consumption traces captured from Multi Core Embedded boards while running the Advanced Encryption Systems(AES) on it b) Implementation of High Speed and High Accurate Prediction learning machines for the prediction of side-channel attacks c) Design of Adaptive Chaotic S-Box using 3-Dlogistic Hyperbolic maps for attacked bits. To evaluate the proposed architecture, experimentation in carried out in an IoT networks and various performance parameters were calculated and analyzed. The results show that the proposed architecture outperforms the other existing algorithms in terms of prediction and performance.