Implementation Of Discrete Fourier Transform Research Articles

Zynq FPGA-Based Acceleration of Kernelized Correlation Filters via High-Level Synthesis of a Custom DFT Block

This study presents a hardware-software co-design implementation of an accelerator for the Kernelized Correlation Filter (KCF) tracking algorithm. Leveraging the High-level synthesis (HLS) and the Zynq heterogeneous platform, the KCF algorithm’s performance is enhanced by using a custom hardware implementation for the computationally intensive Discrete Fourier Transform (DFT) operation. Within this framework, a custom combined DFT and inverse DFT IP, named CDFT, is developed and optimized on the Programmable Logic (PL) side of the Xilinx ZCU102 FPGA, whereas the rest of the KCF algorithm is run with customized Petalinux build on the (Processing System) side. To assess real-world performance, a driver for the CDFT IP and a user application were created to measure metrics like Center Location Error (CLE), Intersection over Union (IoU), and Frame per Second (FPS). The designed DFT accelerator achieves a remarkable speedup of 21x compared to a software DFT implementation. At the algorithm level, the KCF accelerator obtains a 6x speed up with negligible precision loss. In comparison to prior studies employing exclusively hardware implementations, the proposed approach demonstrates a high accuracy at a moderate speed, while there exists potential for further optimizations to enhance its performance even further.

FPGA-based DFT system design, optimisation and implementation using high-level synthesis

In this paper, a discrete Fourier transform (DFT) algorithm is designed and optimised for the FPGA implementation using the Xilinx VIVADO High-Level Synthesis (HLS) tool. The DFT algorithm is written by C++ programming and simulated for functional verification in the HLS and MATLAB. For hardware validation, the DFT module is packaged as an IP core and tested in a VIVADO project. A Xilinx SDK application written by C language is developed and used for testing the DFT module on a Zynq FPGA development board, ZedBoard. For visualisation of the DFT magnitude spectrum generated in FPGA, a GUI is developed by C# programming and related commands/data can be communicated between the GUI and ZedBoard over the serial port. Experimental results are presented with discussion. The DFT module design, optimisation and implementation as well as the VIVADO project development methods can be extended to other FPGA applications.

Large-Scale Discrete Fourier Transform on TPUs

In this work, we present two parallel algorithms for the large-scale discrete Fourier transform (DFT) on Tensor Processing Unit (TPU) clusters. The two parallel algorithms are associated with two DFT formulations: one formulation, denoted as KDFT, is based on the Kronecker product; the other is based on the famous Cooley-Tukey algorithm and phase adjustment, denoted as FFT. Both KDFT and FFT formulations take full advantage of TPU's strength in matrix multiplications. The KDFT formulation allows direct use of nonuniform inputs without additional step. In the two parallel algorithms, the same strategy of data decomposition is applied to the input data. Through the data decomposition, the dense matrix multiplications in KDFT and FFT are kept local within TPU cores, which can be performed completely in parallel. The communication among TPU cores is achieved through the one-shuffle scheme in both parallel algorithms, with which sending and receiving data takes place simultaneously between two neighboring cores and along the same direction on the interconnect network. The one-shuffle scheme is designed for the interconnect topology of TPU clusters, minimizing the time required by the communication among TPU cores. Both KDFT and FFT are implemented in TensorFlow. The three-dimensional complex DFT is performed on an example of dimension 8192 ×8192 ×8192 with a full TPU Pod: the run time of KDFT is 12.66 seconds and that of FFT is 8.3 seconds. Scaling analysis is provided to demonstrate the high parallel efficiency of the two DFT implementations on TPUs.

Reduced hardware costs with software and hardware implementation of digital methods multistage discrete Fourier transform on programmable logic devices

Let us consider questions, which are connected to the research of terms of hardware and software implementation digital signal processing (DSP) methods. Theoretical basis of this research are methods of non-recursive difference of digital filtration with integer difference coefficients different orders of difference and methods of multistage discrete Fourier transform (DFT) based on such digital filtration. The purpose of the study is the research and formalization of necessary and sufficient condition of lowering hardware costs in hardware and software implementation of methods multistage DFT of digital signals on programmable logic devices (PLD). For reaching the research goal there are used methods of direct search and comparative analysis of results of such realization of methods of multi-stage DFT of digital multi-band signals, while filtering these signals, which are based on their non-recursive difference digital filtering with integer difference values coefficients and different orders of magnitude of difference. There are described abilities and specialties of PLD, which are built using architecture of a coarse-grained or fine-grained architecture or using combined architecture, which connects the convenience of implementing digital processing algorithms signals on the basis of tables of code conversion and reconfigurable memory modules. It is clear that a necessary and sufficient condition of lowering hardware costs in terms of hardware and software realization of methods for multi-stage DFT of digital signals on PLD is the triviality of meanings of integer difference coefficients of a non-recursive difference digital high difference orders’ filtration, which ensure this information. There is mentioned a formula, which allows making such condition. The practical significance of the research results consists of defining the necessary and sufficient condition of lowering hardware costs in terms of hardware and software implementation on PLD methods of multi-stage DFT signals based on their non-recursive digital difference filtering with integer values differential coefficients of various orders of magnitude difference. The novelty of research results lies in formalization of this condition. The reliability of the research results confirms their compliance with the results of well-known developments of DSP methods.

Fourier-spectral-method implementation of deformation in the phase-field crystal model

The phase-field crystal (PFC) method is a promising computational model with atomistic resolution and diffusive time scale. In this work, the Fourier-spectral-method (FSM) scheme was developed for evaluating the PFC free energy of a system subjected homogeneous deformation. This scheme addresses the complication where, in numerical implementation of FSM using discrete Fourier transform (DFT), the discretized data may no longer lie along the directions of the Cartesian basis due to deformation. In this scheme, the real-space coordinate transformation is employed so that the (continuous) Fourier transform is performed on the function of the undeformed coordinates. This transformation allows straightforward DFT implementation because the sampling at the undeformed configuration is unaffected by the deformation. This scheme is also shown to be applicable to both the original PFC model and a “CDFT”-type PFC model containing a two-body correlation function.

Implementation of Discrete Fourier Transform And Orthogonal Discrete Wavelet Transform In Python

This paper presents implementation of Discrete Fourier Transform and Orthogonal Discrete Wavelet Transform in Python computer programming language. The Fourier Transform is a fundamental signal processing tool whereas the Wavelet Transform is a powerful and advanced signal processing tool. Both have applications in numerous scientific and engineering disciplines. Our implementation aims to develop a deeper understanding of these transformations by presenting detailed coding steps to generate the frequency-domain and wavelet-domain outputs for selected example time-domain input signals. The results generated from developed program code are compared using built-in functions with similar matches have shown the successful implementation.

Multidimensional DFT IP Generator for FPGA Platforms

Multidimensional (MD) discrete Fourier transform (DFT) is a key kernel algorithm in many signal processing applications. In this paper we describe an MD-DFT intellectual property (IP) generator and a bandwidth-efficient MD DFT IP for high performance implementations of 2-D and 3-D DFT on field-programmable gate array (FPGA) platforms. The proposed architecture is generated automatically and is based on a decomposition algorithm that takes into account FPGA resources and the characteristics of off-chip memory access, namely, the burst access pattern of the synchronous dynamic RAM (SDRAM). The IP generator has been integrated into an in-house FPGA development platform, AlgoFLEX, for easy verification and fast integration. The corresponding 2-D and 3-D DFT architectures have been ported onto the BEE3 board and their performance measured and analyzed. The results shows that the architecture can maintain the maximum memory bandwidth throughout the whole procedure while avoiding matrix transpose operations used in most other MD DFT implementations. To further enhance the performance, the proposed architecture is being ported onto the newly released Xilinx ML605 board. The simulation results show that 2 K × 2 K images with complex 64-bit precision can be processed in less than 27 ms.

Efficient DFT of Zadoff-Chu sequences

Closed-form expressions for the discrete Fourier transform (DFT) of cyclically shifted Zadoff-Chu sequences of arbitrary length are presented. These expressions allow for a very efficient DFT implementation based only on the elements of the corresponding already generated basic (non-cyclically-shifted) ZC sequence.

Low Computational Complexity, Low Power, and Low Area Design for the Implementation of Recursive DFT and IDFT Algorithms

A novel recursive algorithm for discrete Fourier transform (DFT) and its inverse transform (IDFT) is proposed in this brief. It was found that the proposed algorithm and its implementation outperformed other existing recursive algorithms. The proposed algorithm was found to 1) reduce multiplication computations by 50.5% using the symmetric identity of coefficients and a resource-sharing technique and register-splitting scheme; 2) decrease read-only memory sizes by 50% compared with conventional algorithms; 3) reduce the number of multipliers implemented by 80% compared with the latest algorithm; and 4) increase data throughput by 100% per transformation. This design is suitable for communication systems and digital radio mondiale (DRM) systems, such as dual-tone multifrequency detection and coded orthogonal frequency-division-multiplexing modulation. The algorithm was designed and fabricated using a 0.18 ?m 1P6M complementary metal-oxide-semiconductor process. The core area is 397 × 388 ?m2, including the DFT and IDFT modules. For modern applications (voice over packet and DRM), this processor only consumes 2.96 mW at 25 MHz. Furthermore, it can calculate the 212/165/106/288/256/176/112-point DFTs and IDFTs.

Practical Considerations for Recursive DFT Implementation in Numerical Relays

In this paper, practical considerations for recursive Discrete Fourier Transform (DFT) implementation in numerical relays are presented. The DFT filter instabilities which would produce accumulated errors are emphasized. The aspects ruling error accumulation of the estimated magnitude and phase are highlighted. Novel solutions directed for the elimination of error accumulation are proposed and intensively tested. Digital signal processing (DSP) board based test set-up is utilized for the experimental verification. The paper results are valuable for the protection engineers particularly those concerned with the development and implementation of numerical relays

A New Fast Discrete Fourier Transform

This paper presents a new fast Discrete Fourier Transform (DFT) algorithm. By rewriting the DFT, a new algorithm is obtained that uses 2n?2(3n?13)+4n?2 real multiplications and 2n?2(7n?29)+6n+2 real additions for a real data N=2n point DFT, comparable to the number of operations in the Split-Radix method, but with slightly fewer multiply and add operations in total. Because of the organization of multiplications as plane rotations in this DFT algorithm, it is possible to apply a pipelined CORDIC algorithm in a hardware implementation of a long-point DFT, e.g., at a 100 MHz input rate, a 1024-point transform can be realized with a 200 MHz clocking of a single CORDIC pipeline.

On the advantages of the LMS spectrum analyzer over nonadaptive implementations of the sliding-DFT

Based on the least mean squares (LMS) algorithm, the LMS spectrum analyzer can be used to recursively calculate the discrete Fourier transform (DFT) of a sliding window of data. In this paper, we compare the LMS spectrum analyzer with the straightforward nonadaptive implementation of the recursive DFT. In particular, we demonstrate the robustness of the LMS spectrum analyzer to the propagation of roundoff errors, a property that is not shared by other recursive DFT algorithms.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Phase-space localization and discrete representations of wave fields

The high-frequency behavior of wave fields in free space is characterized by localization in phase space, exemplified by the description of geometrical optics in which distinct wave vectors are associated with the rays passing through each spatial point. I explore the manifestation of phase-space localization in discrete representations of the wave field, in particular the discrete Fourier transform (DFT) and the Gabor representation. A number of auxiliary concepts, such as spectral truncation, the Lagrange manifold, and the Landau–Pollak (LP) theorem, are described and exploited in the process of understanding the behavior of high-frequency fields, and it is shown that the Lagrange manifold is the source in phase space of the dominant contributions to these discrete representations in a number of specially selected examples. The LP theorem specifies the number of discrete degrees of freedom required for a given field to be approximated to a prescribed accuracy, and the theorem controls both the number of samples for DFT implementation and the number of Gabor coefficients required. The behavior of the Gabor coefficients away from the Lagrange manifold is studied for a Fresnel wave (quadratic phase variation on a line), and it is shown that these coefficients decay exponentially, signifying the localization of the Gabor representation. The number of operations required for computing the Gabor representation is compared with the fast-Fourier-transform (FFT) implementation of the DFT, with the LP dimension used as the common cardinality of the two representations, the result being that the FFT is asymptotically more efficient than the Gabor representation even after one allows for the localization of the latter. However, the Gabor representation can be used in circumstances in which the FFT is inapplicable, when the explicit localization is a significant advantage.

A neural net approach to discrete Hartley and Fourier transforms

The authors present an electronic circuit, based on a neural (i.e. multiply connected) net to compute the discrete Fourier transform (DFT). They show both analytically and by simulation that the circuit is guaranteed to settle into the correct values within RC time constants (on the order of hundreds of nanoseconds), and they compare its performance to other on-chip DFT implementations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

2D systolic solution to discrete Fourier transform

A number of systolic architectures have appeared over the past few years for performing the discrete Fourier transform (DFT) and fast Fourier transform (FFT) algorithms, using both linear and orthogonal processing networks. The paper shows how a rectangular array of N CORDIC (co-ordinate digital computer) processing elements can be used to carry out an efficient two-dimensional systolic implementation of the N-point DFT, offering highly attractive throughput rates in relation to other N-processor solutions, such as the conventional linear systolic array.

On the effects of varying filter bank parameters on isolated word recognition

The vast majority of commercially available isolated word recognizers use a filter bank analysis as the front end processing for recognition. It is not well understood how the parameters of different filter banks (e.g., number of filters, types of filters, filter spacing, etc.) affect recognizer performance. In this paper we present results of performance evaluation of several types of filter bank analyzers in a speaker trained isolated word recognition test using dialed-up telephone line recordings. We have studied both DFT (discrete Fourier transform) and direct form implementations of the filter banks. We have also considered uniform and nonuniform filter spacings. The results indicate that the best performance (highest word accuracy) is obtained by both a 15-channel uniform filter bank and a 13-channel nonuniform filter bank (with channels spacing along a critical band scale). The performance of a 7-channel critical band filter bank is almost as good as that of the two best filter banks. In comparison to a conventional linear predictive coding (LPC) word recognizer, the performance of the best filter bank recognizers was, on average, several percent worse than that of an eighth-order LPC-based recognizer. A discussion as to why some filter banks performed better than others, and why the LPC-based system did the best, is given in this paper.

On the effects of varying filter bank parameters on isolated word recognition

The vast majority of commercially available isolated word recognizers use a filter bank analysis as the front end processing for recognition. It is not well understood how the parameters of different filter banks (e.g., number of filters, types of filters, filter spacing, etc.) affect recognizer performance. In this talk we present results of performance evaluation of several types of filter bank analyzer in a speaker trained, isolated word recognition test using dialed‐up telephone line recordings. We have studied both DFT (discrete Fourier transform) and direct form implementations of the filter banks. We have also considered uniform and nonuniform filter spacings. The results indicate that the best performance (highest word accuracy) is obtained by both a 15‐channel uniform filter bank and a 13‐channel nonuniform filter bank (with channels spaced along a critical band scale). In comparison to a conventional linear predictive coding (LPC) word recognizer, the performance of the best filter bank recognizers was, on average, several percent worse than that of an eighth order LPC‐based recognizer.