FPGA Implementation Research Articles

Hidden complex multistable dynamical analysis and FPGA implementation of integer-fractional order memristive-memcapacitive chaotic system

Abstract A chaotic circuit based on a magnetic-controlled memristor and charge-controlled memcapacitor is proposed in this paper. The study reveals that it is a hyperchaotic system with hidden characteristics in integer-order. Furthermore, as the parameters change, the attractors exhibit rich evolutionary phenomena. Even after adjusting some parameters to very large values, the system still maintains hyperchaotic behavior. Interestingly, the basin of attraction shows the multistability of the system. Under initial value control, coexisting attractors are categorized into two types: those with initial offset-boosting behavior and nested attractors. When under parameter control, coexisting attractors are divided into two types: symmetric coexisting attractors and nested coexisting attractors. By analyzing the spectral entropy (SE) complexity of the system and using a complexity distribution diagram with two parameters and two initial values, the existence of multiple complex dynamic behaviors in the system has been verified. The fractional-order memristive-memcapacitive system based on the Grunwald-Letnikov algorithm and the five fractional-order values of q i (i = 1, 2, 3, 4, 5) are taken as different in the numerical simulation, it also displays multiple coexisting phenomena similar to those of the integer-order. Finally, Matlab/Simulink and DSP Builder software platform are used to design the fractional-order five-dimensional chaotic memristive-memcapacitive system, and then combined with VHDL and Verilog HDL hardware language, the proposed circuit system is verified on the EP4CE115F29C7 FPGA main chip of Cyclone IV E series. The consistency of hardware implementation and software simulation shows the correctness and feasibility of the design.

Comprehensive Survey of Image Steganography Systems based on FPGA Implementation

Steganography is the art of concealed communication. The basic idea of steganography is to hide secret data inside a cover media in an undetectable manner. Cover media and Secret data can be any popular digital media such as image, video, audio, or text. Various types of image steganography methods have been proposed according to the cover image domain, i.e. spatial domain and transform domain. The spatial domain methods are easy and simple while the transform domain methods are more complex. However, the transform domain methods are more robust against image processing operations. Besides, they are more secure and less detectable in an unsecured channel. The recent steganography methods are based on sophisticated algorithms that include several computational time-consuming tasks, and hence they are unable to embed and extract the hidden data in real-time. Therefore, the trend is to implement the steganography methods in the hardware to speed up their processing time and so improves the efficacy of steganography techniques. FPGA is used in various fields in the modern era due to lower development cost, flexibility, and reconfigurability. Most of the published steganography techniques carried out on FPGA are based on the spatial domain. In this paper, it has comprehensively studied and reviewed various existing implementations of image steganography on FPGAs. This includes studying their general operations, requirements, and performance evaluations. This review would assist researchers in finding the research gaps in FPGA implementation of steganography methods for real-time applications.

FPGA implementation of an optimized neural network for CFD acceleration

In this work, an evaluation of FPGAs as the central computation platform in domain-specific AI-accelerated CFD simulations is performed. This evaluation is performed in three categories: power efficiency, speed, and accuracy. The specific domain in the study is the FDA nozzle benchmark, which is simulated using SimpleFoam, a laminar solver that is a component of the OpenFOAM CFD toolbox. The proposed AI model is a low-parameter feed-forward neural network with three fully connected layers, trained using steady-state solutions distinguished by various Reynolds numbers, all of which are computed by the OpenFOAM framework. The proposed model can then generate the steady-state CFD simulation result given the initial few iterations generated by the solver. Moreover, this paper introduces a hardware implementation for inference of the simulation results using an SoC chip with minimal hardware resource utilization. The suggested hardware design is developed from scratch for Zynq-7000 System-on-Chip, using only VHDL, and requiring no dependencies on third-party commercial AI frameworks or costly FPGA boards designed for AI-related applications. The proposed workflow in the test case study achieves a 98% reduction in simulation time while maintaining relatively high accuracy and a 95.6% reduction in energy consumption compared with the regular CFD workflow.

Design and FPGA implementation of encrypted frame transmission scheme based on chaotic reverse synchronization

Design and FPGA implementation of encrypted frame transmission scheme based on chaotic reverse synchronization

Hardware Area Efficiently and Real-Time FPGA Implementation of PHMMRGB

For encryption applications on embedded systems, operating in real-time while using minimal system resources is essential. It is expected that efficient and rapid encryption of high-resolution images is to be accomplished with limited hardware resources. Therefore, in order to ensure the desired efficiency of encryption of high-resolution images, the system must possess a digital architecture capable of achieving high speeds with minimal hardware resources. This study considered the limitations of a hardware architecture for an image encryption algorithm based on the Profile Hidden Markov Model called PHMMRGB. The proposed architecture is relatively simple in comparison to its alternatives. The hardware architecture, designed with the objective of using minimal resources, has been implemented on an FPGA. Based on the results of the proposed architecture, it is believed that the implementation of the specified method on an FPGA would yield high efficiency. Experiments conducted using large-sized satellite images confirmed this expectation.

FPGA Implementation for a Class of Generalized Hamiltonian Conservative Chaotic Systems Based on Integrated 4D Euler Equations with Multistability

In this paper, two newly proposed generalized Hamiltonian Conservative Chaotic Systems (CCSs) based on integrated 4D Euler equations are first discussed. Second, another generalized Hamiltonian CCS is also proposed. Furthermore, a class of generalized Hamiltonian CCSs based on integrated 4D Euler equations is given and studied. Subsequently, numerical analysis for the class of generalized Hamiltonian CCSs is further investigated to show their advantages over most of the existing CCSs, where the corresponding Lyapunov exponents’ diagrams, bifurcation diagrams and phase portraits are all given to show their multistability and complex dynamics. Finally, the class of generalized Hamiltonian CCSs is implemented by using FPGA technology, and the results observed in FPGA implementation are consistent with those observed in the numerical analysis. All these results not only show multistability from a physical point of view, but also provide new physical models for chaos applications.

FPGA Implementation of Compact Architecture for Lightweight Hash Algorithm for Resource Constrained Devices

The security implications of the emerging world of smart devices brought about by the Internet of things' recent rise are enormous. IoT devices typically have restricted resources, such as minimal memory, low processing power, and a short battery life, in addition to their stated security level. In the context of IoT, lightweight cryptographic primitives are presented taking into account the trade-off between speed and security assurance. In this research, we proposed lightweight cryptographic hash methods and optimized hardware for devices with limitations. The size, speed, efficiency, and power consumption of our suggested solutions are examined on FPGA systems. Bit permutation, linear transformation, and S-Box functionality are used in the suggested design. To analyze large data sets and Internet of Things applications, conventional hash algorithms need memory and time. Thus, the demand arises for a lightweight cryptographic protocol that is both rapid and safe. This technique offers the necessary security criteria of conventional hash functions and the parameters for lightweight cryptographic protocols. The proposed architecture is tested and validated based on three key criteria: memory, speed, and power consumption, which are important factors in determining its lightweight nature. Based on the findings, the proposed architecture outperforms other lightweight protocols regarding memory usage, performance, and power consumption. For an appropriate FPGA-based application deployment, a thorough comparison of our suggested designs is detailed on various FPGA families.

Design and implementation of low power multiplierless FIR filters on FPGA and ASIC

ABSTRACT This paper presents a low-power design and implementation approach for multiplierless FIR filters by reducing switching activity between filter coefficients using different optimisation algorithms. The objective function simultaneously minimises hamming distance between the consecutive filter coefficients, passband, and stopband ripples. Low-pass, high-pass, band-pass, and band-stop FIR filters of different order and word lengths are designed using improved grey-wolf optimisation. Comparison with grey-wolf optimisation, hybrid particle swarm optimisation, and grey-wolf optimisation, and whale optimisation algorithms is performed for different statistical parameters. The proposed filter is also compared with existing filter designs and shows considerable improvement in design metrics. For low-power implementation of designed FIR filters, carry-save-adder trees are utilised. FPGA and ASIC platforms are used for implementation. Basys-3 (Artix-7) FPGA board is targeted using the Vivado tool for FPGA implementation. Hardware design metrics such as slice LUTs, slice registers, slices, and dynamic power consumption are obtained. ASIC implementation is also performed using the Cadence Genus tool for a 45 nm Nan gate open cell library and total area, power, and delay are reported. The obtained results for FPGA slice utilisation and power consumption provide an average reduction of 61.39% and 74.13%, respectively. ASIC implementation provides an average 58.60% reduction in area-power product.

A Computation of the Ninth Dedekind Number Using FPGA Supercomputing

This manuscript makes the claim of having computed the \(9\) th Dedekind number, D(9). This was done by accelerating the core operation of the process with an efficient FPGA design that outperforms an optimized 64-core CPU reference by 95 \(\times\) . The FPGA execution was parallelized on the Noctua 2 supercomputer at Paderborn University. The resulting value for D(9) is 286386577668298411128469151667598498812366. This value can be verified in two steps. We have made the data file containing the 490 M results available, each of which can be verified separately on CPU, and the whole file sums to our proposed value. The paper explains the mathematical approach in the first part, before putting the focus on a deep dive into the FPGA accelerator implementation followed by a performance analysis. The FPGA implementation was done in Register-Transfer Level using a dual-clock architecture and shows how we achieved an impressive FMax of 450 MHz on the targeted Stratix 10 GX 2,800 FPGAs. The total compute time used was 47,000 FPGA hours.

FPGA Implementation and Performance Analysis of Parallel Prefix Structures for Modular Adders Design

FPGA Implementation and Performance Analysis of Parallel Prefix Structures for Modular Adders Design

CSAIL2019 Crypto-Puzzle Solver Architecture

tThe CSAIL2019 time-lock puzzle is an unsolved cryptographic challenge introduced by Ron Rivest in 2019, replacing the solved LCS35 puzzle. Solving these types of puzzles requires large amounts of intrinsically sequential computations, with each iteration performing a very large (3,072-bit for CSAIL2019) modular multiplication operation. The complexity of each iteration is several times greater than known field-programmable gate array (FPGA) implementations, and the number of iterations has been increased by about 1,000x compared with LCS35. Because of the high complexity of this new puzzle, a number of intermediate, or milestone, versions of the puzzle have been specified. In this article, we present several FPGA architectures for the CSAIL2019 solver, which we implement on a medium-sized Intel Agilex device. We develop a new multi-cycle modular multiplication method, which is flexible and can fit on a wide variety of sizes of current FPGAs. We introduce a class of multi-cycle squarer-based architectures that allow for better resource and area trade-offs. We also demonstrate a new approach for improving the fitting and timing closure of large, chip-filling arithmetic designs. We used the solver to compute the first 23 out of 28 milestone solutions of the puzzle, which are the first reported results for this problem.

Development of Digital Image Processing Algorithms via FPGA Implementation

Real-time image processing is one of the fundamental elements in achieving IR 4.0. The rapid development of digital image processing techniques has enabled various applications in fields such as healthcare, transportation, and manufacturing. People are seeking higher-performance image processing as traditional image processing is no longer fulfilling the demands. FPGA-based digital image processing has become one of the choices for the public due to its parallel pipelining, which enables shorter processing time and better performance. Several digital image processing algorithms have been developed in this project, which are gray level transformation, brightness manipulation, contrast adjustment, thresholding, and inversion. They are the most popular algorithms used in digital image processing. Microsoft Paint is used to convert the format of the color input image to bitmap format, followed by MATLAB to convert it into a hexadecimal file to be read and written in FPGA. Platforms such as ModelSim Altera and Intel Quartus II are used to write Verilog HDL for digital image processing algorithms. As a result, five hexadecimal files are obtained from the simulation. The output hexadecimal files are further processed in MATLAB to generate respective images.

Enhanced lightweight encryption algorithm based on chaotic systems

In order to improve security and efficiency, this study presents a novel lightweight encryption technique that makes use of chaotic systems. Our method creatively combines the new chaotic KLEIN_64 algorithm with the Keccak-256 hash function, offering a solid basis for producing initial values essential for causing chaotic maps during the encryption process. After a deep validation with rigorous NIST testing, our chaotic pseudo random generator, LAC, exhibits excellent reliability and cryptographic robustness. Furthermore, the complexity of the cryptographic round function is improved by incorporating a second chaotic pseudo random generator that combines chaotic LFSR and Skew Tent Maps, thereby fortifying security measures.Designed with resource-limited applications in mind, our approach ensures that the cryptosystem remains both lightweight and efficient, meeting the stringent constraints typical of such environments. The practical feasibility and performance of our approach are extensively evaluated through FPGA implementation on the Zybo 7Z010 platform. Our implementation achieves a remarkable throughput of 2.820 Gbps while maintaining optimal resource utilization and efficiency. Extensive experimental results confirm the superior security of our cryptosystem, with correlation tests, entropy measurement, and histogram analysis showcasing robustness against statistical attacks. Moreover, the cryptosystem shows little fluctuation in the Unified Average Changing Intensity (UACI) and Non-Linear Pixel Change Rate (NPCR), confirming its resistance to differential attacks. Overall, our technique advances lightweight cryptography by providing a robust and efficient solution to modern cybersecurity challenges. In particular, our approach is well-suited for applications with limited resources, ensuring that security is maintained without compromising on performance or efficiency, thus fulfilling the needs of modern, constrained environments.

Design and FPGA implementation of nested grid multi-scroll chaotic system

Conventional multi-scroll chaotic systems are often constrained by the number of attractors and the complexity of generation, making it challenging to meet the increasing demands of communication and computation. This paper revolves around the modified Chua’s system. By modifying its differential equation and introducing traditional nonlinear functions, such as the step function sequence and sawtooth function sequence. A nested grid multi-scroll chaotic system (NGMSCS) can be established, capable of generating nested grid multi-scroll attractors. In contrast to conventional grid multi-scroll chaotic attractors, scroll-like phenomena can be initiated outside the grid structure, thereby revealing more complex dynamic behavior and topological features. Through the theoretical design and analysis of the equilibrium point of the system and its stability, the number of saddle-focused equilibrium points of index 2 is further expanded, which can generate (2 N+2) × M attractors, and the formation mechanism is elaborated and verified in detail. In addition, the generation of an arbitrary number of equilibrium points in the y-direction is achieved by transforming the x and y variables, which can generate M×(2 N+2) attractors, increasing the complexity of the system. The system’s dynamical properties are discussed in depth via time series plots, Lyapunov exponents, Poincaré cross sections, 0–1 tests, bifurcation diagrams, and attraction basins. The existence of attractors is confirmed through numerical simulations and FPGA-based hardware experiments.

A Review of ECG Classification Techniques Based FPGA

Electrocardiogram (ECG) signals are particularly used in the diagnosis and supervision of different cardiovascular diseases. The accurate and efficient classification of ECG signals is of critical importance in clinical applications. FPGA-based systems have been identified to offer an efficient solution to the implementation of real-time ECG signal classification systems because of their parallel processing, reprogrammable nature, and low power consumption. Thus, this review paper aims to explore the existing ECG classification techniques with a focus on FPGA implementation. The review discussed several classification methods, including adaptive algorithms and neural networks, which have been optimized for arrhythmia detection. Notably, Neural network techniques like ANN, CNN, and spiking neural networks are preferable due to their ability to provide superior accuracy. For instance, Mathias et al. developed a high-precision neural network with an impressive accuracy of 99.82%. Similarly, Arona et al. deployed a DCNN on FPGA, achieving accuracies reaching up to 99.67%. Researchers widely used the MIT-BIH dataset to evaluate ECG classification techniques, This paper presents new trends and focuses on future research prospects in this field. Hence, the findings of the present review can help researchers and engineers in developing effective and efficient FPGA-based ECG monitoring and diagnostic systems for clinical and healthcare applications.

Novel Minimalist Hardware Architecture for Long Sync Word Frame Synchronization and Payload Capture

Sync word-based frame synchronization is an established method of frame synchronization that is employed in many low-resource applications because of its simplicity, and it involves the attachment of sync words (digital binary sequences) to the frames, which are then used for detection. Despite its simplicity, the method is underutilized today because there is no available hardware scheme that can perform correlation-based sync word frame synchronization with long sync words (>80 bits) efficiently. For this reason, the sync word methods that are used typically employ sync words of shorter lengths (<50 bits) with limited accuracy. This article introduces a highly modifiable, minimalist hardware architecture that performs correlation-based sync word frame synchronization using long sync words with evident accuracy gains over existing methods. As a bonus, the architecture not only detects the frame but also captures its payload regardless of size. Its low complexity allows for its deployment at a low cost in terms of hardware resources and power while providing high bit rates. Its flexibility is demonstrated by using a low-cost FPGA for implementation.

High-bandwidth FPGA based randomized voltage states for controlling optoelectronic devices in QKD systems

We have developed an inexpensive system for generating random voltage states (RVS) on a FPGA platform. This system can be used for controlling optoelectronic devices in a quantum-key-distribution (QKD) system. We use an all-digital operation at the FPGA layer to generate two uncorrelated Boolean bit strings. These bit strings are converted to RVS using a multiplexer and a voltage buffer in order to drive commercially available optoelectronic devices. A National Instruments (N.I) real-time IO (RIO) platform was used for FPGA implementation. The FPGA layer was coupled to the desktop layer for real-time monitoring and logging of the Boolean bit strings. We characterize the performance of the multiplexer and the buffer and describe how their engineering performance trades-off with the fidelity of RVS generation.

AES 32: An FPGA implementation of Lightweight-AES for IoT Devices

AES 32: An FPGA implementation of Lightweight-AES for IoT Devices

Design and FPGA Implementation of Signal Strength Measurement Techniques for Satellite Communication Systems

Communication receivers perform three major functions, frequency down conversion, IF demodulation and subcarrier demodulation. The functioning of a receiver is mainly controlled by input signal strength and relative dynamics. Signal strength is measured in terms of Signal to Noise ratio (SNR) and Carrier to Noise power density (C/No). Any measure of signal strength indirectly gives information about receiver performance for that period. Apart from this, SNR measurement in close loop with Phase Locked Loop (PLL) parameter forms the adaptive PLL system, which is one of the driving forces for this paper. The focus of this paper is to find suitable signal strength measurement techniques and their implementation for satellite communication systems. Signal to Noise Variance method (SNV) and Narrow band Wide band Power Ratio (NWPR) methods are considered based on the performance and realization aspects. All techniques require division, logarithm, and multiplication functions for their realization in hardware. CO-ordinate Rotation Digital Computer (CORDIC) algorithm is considered for realizing logarithm function. A comparison study is done for developed algorithm with Intellectual Property (IP) core. Developed SNR techniques are simulated for Binary Phase Shift Keying (BPSK) demodulator system and performance is evaluated for Additive White Gaussian Noise (AWGN). The paper describes the FPGA design and simulations of these techniques. Developed design is targeted to commercial and space qualified FPGA platforms. FPGA implementations results are compared with system level simulation results, and both are found to be satisfactory. Application of developed system in adaptive BPSK demodulator is also presented.

FPGA implementation of Hopfield neural network with transcendental nonlinearity

FPGA implementation of Hopfield neural network with transcendental nonlinearity