Impact Of Threshold Voltage Variation Research Articles

Impact of threshold voltage variation on 1S1R crossbar array with threshold switching selectors

It is important that selector achieves voltage compatibility with paired resistive random access memory element. Nevertheless, unsatisfactory uniformity existing in practical selector devices will lead to serious problems during operation. This paper investigates the potential impact of threshold voltage variation on crossbar array with one-selector one-resistor cell. We prove that large variation of threshold voltage may lead to unintentional writing during read process. Therefore, we propose a method to determine selectors’ threshold voltage range within 1/2 or 1/3 bias scheme. Results indicate tolerable threshold voltage range basically expands with the increasing OFF-resistance or decreasing ON-resistance of selectors. The proposed method gives a guideline for choosing and fabricating appropriate selectors for RRAM elements with specific parameters.

Study of Random Variation in Germanium-Source Vertical Tunnel FET

An optimally designed germanium-source vertical tunnel FET (V-TFET) is investigated using technology computer aided design simulation. Three consecutive band-to-band tunneling (BTBT) mechanisms (i.e., lateral, vertical, and additional vertical BTBT) are used in the V-TFET to enhance its performance as well as to maintain an average subthreshold slope below 60 mV/decade at 300 K. The impact of various V-TFET parameters on its performance is also investigated. Furthermore, the impact of threshold voltage variation ( $\sigma V_{\textrm {TH}}$ ) due to random variability [e.g., line-edge roughness (LER) and random dopant fluctuation (RDF)] on the performance of the V-TFET is studied. The LER in the V-TFET is found that the electric field is increased by the LER in the source region, resulting in the generation of lucky paths, which can lead to increase $\sigma V_{\textrm {TH}}$ . Without a gate-to-source overlap region in the V-TFET, RDF/LER-induced $\sigma V_{\textrm {TH}}$ is considerably increased by a lateral tunneling mechanism. As a result, the gate-to-source overlap region in the V-TFET is critical to enhancing the performance and designing a variation-aware V-TFET. Last but not least, field-induced quantum confinement leads to delay the onset voltage of the vertical BTBT, so that the device performance and process-induced random variation (especially, RDF) are significantly deteriorated.

The evolution of standard cell libraries for future technology nodes

Evolvable Hardware has been a discipline for over 15 years. Its application has ranged from simple circuit design to antenna design. However, research in the field has often been criticised for not addressing real world problems. Intrinsic variability has been recognised as one of the major challenges facing the semiconductor industry. This paper describes an approach that optimises designs within a standard cell library by altering the transistor dimensions. The proposed approach uses a Multi-objective Genetic Algorithm to optimise the device widths within a standard cell. The designs are analysed using statistically enhanced transistor models (based on 3D-atomistic simulations) and statistical Spice simulations. The goal is to extract high-speed and low-power designs, which are more tolerant to the random fluctuations present in current and future technology nodes. The results show improvements in both the speed and power of the optimised standard cells and that the impact of threshold voltage variation is reduced.

Optimizing electronic standard cell libraries for variability tolerance through the nano-CMOS grid

The project Meeting the Design Challenges of nano-CMOS Electronics (http://www.nanocmos.ac.uk) was funded by the Engineering and Physical Sciences Research Council to tackle the challenges facing the electronics industry caused by the decreasing scale of transistor devices, and the inherent variability that this exposes in devices and in the circuits and systems in which they are used. The project has developed a grid-based solution that supports the electronics design process, incorporating usage of large-scale high-performance computing (HPC) resources, data and metadata management and support for fine-grained security to protect commercially sensitive datasets. In this paper, we illustrate how the nano-CMOS (complementary metal oxide semiconductor) grid has been applied to optimize transistor dimensions within a standard cell library. The goal is to extract high-speed and low-power circuits which are more tolerant of the random fluctuations that will be prevalent in future technology nodes. Using statistically enhanced circuit simulation models based on three-dimensional atomistic device simulations, a genetic algorithm is presented that optimizes the device widths within a circuit using a multi-objective fitness function exploiting the nano-CMOS grid. The results show that the impact of threshold voltage variation can be reduced by optimizing transistor widths, and indicate that a similar method could be extended to the optimization of larger circuits.