Impact Of Gate Resistance Research Articles

Impact of Gate Resistance on Improving the Dynamic Overcurrent Stress of the Si/SiC Hybrid Switch

A silicon/silicon carbide (Si/SiC) hybrid switch (HyS), comprised of a high-current Si insulated gate bipolar transistor and a low-current SiC metal oxide semiconductor field effect transistors, gains attention because it offers lower <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -state loss under both light and heavy loads. However, the dynamic overcurrent stress experienced by the HyS under the heavy load has to be coped with to avoid reliability degradation and the maximum current rating limitation. This article comprehensively studies how gate resistances regulate the dynamic behavior of the HyS under the heavy load condition. Experiments and analyses are conducted for both turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> and turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> processes. It is found that the gate resistance is important for not only the d <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</i> /d <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> control but also the overcurrent suppression. Moreover, the lower switching loss can be achieved by adjusting gate resistances when the HyS operates at a heavy load, compared with the gate timing control. A guideline is developed for the design of the gate resistances. This study offers an insight into the role of gate resistances in switching performances of the HyS and an alternative way of coping with the dynamic overstress stress.

Analytical Study of SiC MOSFET Based Inverter Output dv/dt Mitigation and Loss Comparison With a Passive dv/dt Filter for High Frequency Motor Drive Applications

Fast switching characteristic of wide bandgap devices enables high switching frequency of power devices and thereby, can facilitate high fundamental frequency operation of electrical machines. However, with the switching transition times in orders of tens of nanoseconds, the high dv/dt is observed across the switching device. The high dv/dt experienced by the switches, and consequently by the machine, can degrade winding insulations or bearings over a period of time. Therefore, it is imperative to maintain the dv/dt below recommended values depending on the machine insulation. The dv/dt across the devices can be adjusted by varying the gate resistance. A high value of gate resistance, however, introduces additional switching losses on the device. Using different dv/dt filtering techniques can also help to control the dv/dt on the machine terminals. These techniques do not increase the switching losses on the device. However, it introduces additional losses in the filter resistors and also increases the cost of the system. In this paper, an analysis based on the impact of gate resistance on the dv/dt across the machine, and the corresponding losses is carried out. An analytical dv/dt filter design strategy is proposed to limit the dv/dt to a particular value. With the proposed design scheme, the value of each filter component can be easily obtained, and filter losses can be estimated accurately. Lastly, a comparison is performed on the basis of efficiency between these two techniques.

Impact of gate resistance in graphene radio frequency transistors

The effect of gate resistance on the high frequency device properties of graphene transistors is explored. Decreasing this resistance does not alter the current gain cutoff frequency (fT), but it does allow for the power gain cutoff frequency (fmax) to be increased. Analysis of this effect reveals that the relative rate of change between fT and fmax is most sensitive to the relationship between the parasitic resistance in the device channel and the output conductance, a manifestation of device scaling in the triode regime. This result underlies the importance of a small output conductance in the scaling of graphene transistors.

A High-Dynamic Range Current Source Gate Driver for Switching-Loss Reduction of High-Side Switch in Buck Converter

In this letter, a high-dynamic range current source gate driver (HD-CSD) circuit is proposed to reduce the switching loss of the high-side switch in buck converter with wide variation of the gate resistance. Hard switching loss is the major loss in high-side switch and limits the high switching-frequency application of dc-dc converter. Comparing with conventional voltage source gate driver (VSD) and the reported four switches CSD (4S-CSD), the proposed HD-CSD behaves more like the ideal current source driver which can realize the fast switching of power switches to reduce the switching loss. In addition, with proposed HD-CSD, impact of gate resistance that limits the switching speed of the power switch can be greatly reduced. Experimental results are presented to show the power efficiency improvement of buck converter with HD-CSD high-side driver comparing with VSD and 4S-CSD high-side drivers at switching frequency of 1 MHz.

High frequency noise of MOSFETs I Modeling

In this paper, a model is proposed which can predict accurately both ac and noise performance (all four noise parameters: minimum noise figure NF min, equivalent noise resistance R n, optimized source resistance R opt and reactance X opt) of MOSFETs based on s-parameter and noise measurements at microwave frequencies. This model includes the relevant high frequency noise sources (i.e. the channel thermal noise, the induced gate noise and its correlation with the channel thermal noise and the thermal noise from the gate and parasitic resistances). In order to confirm the accuracy of the model and obtain the intrinsic scattering and noise parameters of devices, two de-embedding techniques (probe pad equivalent circuit modeling and direct parasitic noise de-embedding) have been used to de-embed the probe pad parasitics from the measured noise and s-parameters of the device-under-test (DUT). In addition, because of the complexity of this noise model, a direct calculation technique for calculating the four noise parameters was developed based on the small-signal transistor's model. Finally, the impact of gate resistance, and the noise improvement using multi-finger gate design are investigated.

Direct calculation of metal–oxide–semiconductor field effect transistor high frequency noise parameters

This article presents, for the first time, a method to directly calculate the noise parameters (minimum noise figure NFmin, equivalent noise resistance Rn, and optimized source resistance Ropt and reactance Xopt) of metal–oxide–semiconductor field effect transistors based on the HSPICE level 3 model because all the model parameters are available from the manufacturer of our device-under-test. All physically based high frequency noise sources, thermal noise from the channel, gate, source and drain resistances, induced gate noise, and the correlation among them, are considered, and the impact of gate resistance and induced gate noise on the noise parameters is studied. The method of direct calculation of noise parameters can be applied to any sophisticated small-signal device model.