Junctionless transistors (JLTs) have promising advantages such as structural simplicity without p-n-junctions and bulk conduction-based operation for the realization of advanced complementary metal oxide semiconductor (CMOS) technologies. Here the channel-length dependence on the operation of JLTs with substrate biasing (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gb</sub> ) was investigated in detail. Parasitic series resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sd</sub> ) noticeably decreased as V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gb</sub> increased. In addition, transconductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ), its derivative (dg <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> /dV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gf</sub> ), and ON-drain current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ) in a short-channel JLT were significantly affected by the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gb</sub> -modulated R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sd</sub> with charge coupling effects. This work provides important information for better understanding and true estimation of intrinsic JLT performance, for practical applications based on polycrystalline Si, III-V semiconductors, and transition metal dichalcogenides (TMDs) nano-materials as well as advanced logic devices.