IEEE P1149 Research Articles

A new die-level flexible design-for-test architecture for 3D stacked ICs

A die-level design-for-test architecture for 3D stacked ICs is proposed. The main component of this architecture is a newly proposed configurable boundary cell, based on which flexible parallel test is achieved. Both of the number of parallel scan chains and their lengths can be configured during test. This test architecture features light-weight, high flexibility in parallel test configuration, modularity, and IEEE P1149.1 compatibility. In this work, both infrastructure and implementation aspects are illustrated. Experimental results demonstrate desired test acceleration. The acceleration ratio approximately reaches its limit, which equals the number of parallel scan chains, when the number of test vectors is over 300.

Overview of Debug Standardization Activities

This article presents an overview of the goals and activities of five debug standardization bodies: the Nexus 5001, MIPI (Mobile Industry Processor Interface) Test and Debug, IEEE P1149.7, IEEE P1687, and OCP-IP (Open Core Protocol International Partnership) Debug working groups. The article also describes the relation between these various activities and discusses their standardization plans for the near future.

P1149.4 Mixed-Signal Test Bus

The IEEE P1149.4 Mixed-Signal Test Bus Working Group has been busy developing a usable standard addressing analog testability issues for mixed-signal technologies. The Working Group's charter is to define, document, and promote the use of a standard mixed-signal test bus that can be used at the device and assembly levels to improve the controllability and observability of mixed-signal designs and to support mixed-signal built-in self-test structures in order to reduce test development time, testing costs, and improve test quality.This short article will update the reader with the current standard architecture proposal, explain how the architecture can be used in a test scenario, and challenge the reader to respond to the Working Group with solutions or observations concerning some current topics of debate within the group. This standard is still in the stages of finalization, and the ideas and constructs presented here are proposals generally accepted by the Working Group, but may still change for technical or other reasons.

Cost/benefit analysis of the P1149.4 mixed-signal test bus

After briefly describing the proposed IEEE P1149.4 mixed-signal test bus standard and its salient benefits, the author investigates detailed costs of implementing the standard on ICs. The benefits include continuous time access in voltage and current mode, measurement of parameters such as resistance, capacitance and delay, and true differential access. The cost increase can vary between 3 and 35%, depending on the initial die size and whether 1149.1 is already on the IC. Lastly, proposed alternatives and future acceptance are discussed.

Off-chip I ddq monitor with standardtest interface

Off-chip current testing is being considered as an efficient mechanism for improving the quality of electronic systems at the printed circuit board level. This well known fact is linked with the industry accepted testing interface standard IEEE P1149.1 (‘Standard test access port and boundary-scan architecture’). A specific integrated circuit with the capability of concurrently measuring the quiescent current level for two integrated circuits under test (ICCUT) is presented with its basis, architecture and implementation details. All the functions of the monitors are accessible via the standard test access port.

Shared-I/O scan test

The IEEE P1149.2 standard seeks to implement several new features, such as shared-I/O cells, an optional parallel-update stage, and a high-impedance input pin. Although aspects of these features are incompatible with IEEE Std 1149.1, the working group strives to make P1149.2 consistent with the existing standard's primary goals.

IEEE P1149.5 Module Test and Maintenance Bus

The objectives and intended uses of the proposed IEEE P1149.5 Module Test and Maintenance Bus standard are reviewed. Design-for-test features being used in component designs to aid in component, board, subsystem, and system test and maintenance are reviewed. The relationship of the IEEE P1149.5 MTM bus to other test buses is outlined, and the operation protocol is described. Extensions of the standard to meet the needs of specifications are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Boundary-scan update-IEEE P1149.2 description and status report

The IEEE P1149.2 Working Group is developing a standard that supports boundary scan for board-level interconnect testing and supports internal scan for device- or board-level component testing. The group's overall objective is to establish minimal mandatory features that are adaptable to individual applications. P1149.2's current status and the most recent proposals being considered for the standard are described. >