IEEE International Solid-State Circuits Conference Research Articles

Guest Editorial Selected Papers From the 2023 IEEE International Solid-State Circuits Conference

Guest Editorial Selected Papers From the 2023 IEEE International Solid-State Circuits Conference

Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC)

Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC)

Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC)

Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC)

Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC)

The International Technical Program Committee (ITPC) of the IEEE International Solid-State Circuits Conference (ISSCC) selects outstanding articles from the papers presented at the conference and invites the authors to submit an extended manuscript to the special issue of IEEE Journal of Solid- State Circuits (JSSC). This January issue contains the selected papers from the Digital Architectures and Systems, Digital Circuits, Machine Learning, Memory, and Wireline subcommittees.

IEEE SSCS Student and Young Professionals Mentoring Event at ISSCC 2023 [Society News

The Solid-State Circuits Society (SSCS) Young Professionals (YP) and Students Micro-Mentoring and Networking event was held on the evening of 21 February 2023 in San Francisco in accordance with the IEEE International Solid-State Circuits Conference (ISSCC). The event was held in person for the first time after three years. More than 70 attendees who chose to be mentors or mentees enjoyed food, drink, and friendly conversation at this flagship event organized by IEEE Solid-State Circuits Society (SSCS) YP Committee members Alireza Yousefi and SSCS YP chair Korkut Kaan Tokgoz.

Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC)

This Special Issue of the IEEE JOURNAL OF SOLID-STATE CIRCUITS presents a collection of the best papers selected from the 2022 IEEE International Solid-State Circuits Conference (ISSCC) that took place in a virtual format from 20 February until 24 February 2022. This issue covers articles from the RF, Wireless, Analog, Data Converters, and Power Management subcommittees.

Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC)

The International Technical Program Committee (ITPC) of the IEEE International Solid-State Circuits Conference (ISSCC) selects outstanding articles from the papers presented at the conference and invites the authors to submit an extended manuscript to the Special Issue of IEEE Journal of Solid-State Circuits (JSSC). This November issue contains the selected papers from the Imagers, microelectromechanical systems (MEMS), and Displays (IMMD) and the Technology Directions (TD) sub-committees. Papers from Analog, Data Converters, Power Management, RF, and Wireless subcommittees are included in the December issue. Finally, the January issue will contain papers from Digital Architectures and Systems, Digital Circuits, Machine Learning, Memory, and Wireline subcommittees.

Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC)

This Special Section of the IEEE Journal of Solid-State Circuits is dedicated to a collection of the best articles selected from the 2021 IEEE International Solid-State Circuits Conference (ISSCC) that took place on February 13–22, 2021, in San Francisco, CA, USA. This Special Section covers articles from the Wireline, Digital Circuits, Digital Architectures and Systems (DASs), Machine Learning and AI, and Memory Committees.

Guest Editorial Introduction to the Special Issue on the 2021 IEEE International Solid-State Circuits Conference (ISSCC)

This Special Issue of the IEEE Journal of Solid-State Circuits is dedicated to a collection of the best papers selected from the 2021 IEEE International Solid-State Circuits Conference (ISSCC) that took place on February 13-22, 2021, virtually. This issue covers papers from the Analog, Power Management, Data Converters, RF, and Wireless committees.

Guest Editorial Selected Papers from the 2021 IEEE International Solid-State Circuits Conference

The papers in this special section were presented at the 2021 IEEE International Solid-State Circuits Conference.

Guest Editorial Introduction to the Special Issue on the 2021 IEEE International Solid-State Circuits Conference (ISSCC)

The International Technical Program Committee (ITPC) of the IEEE International Solid-State Circuits Conference (ISSCC) selects outstanding articles from the papers presented at the conference and invites the authors to submit a manuscript to the special issue of IEEE Journal of Solid-State Circuits (JSSC). The manuscripts offer extended materials such as in-depth circuit descriptions, more experimental results, and benchmarking data. The manuscripts subsequently undergo a rigorous review process. This November issue contains the selected papers from the Imagers, MEMS, and Displays (IMMD) and the Technology Directions (TD) subcommittees. Papers from Analog, Data Converters, Power Management, RF, and Wireless subcommittees are included in the December issue. Finally, the January issue will contain papers from Digital Architectures and Systems, Digital Circuits, Machine Learning, Memory, and Wireline subcommittees.

Stacked Diodes for Pulsed Power Applications: New Process Integration Scheme

Since Boff, Moll, and Shen’s discovery of the high-speed switching effect inherent in initially forward-biased silicon diodes that are suddenly reverse-biased in 1960 [1]; DSRD’s (as termed by Grekhov and Kardo-Sysoev in 1985 [2]) performance has not increased as their deep-diffusion manufacturing process remains the same as it was over 60 years ago. Albeit new pulse generator topologies which utilize diodes like DSRDs, i.e., SOS diodes (termed by Rukin in 1992 [3]) have shown improvement at circuit level given they operate under a higher direct-current density compared to that of DSRD-based pulsers – the voltage-to-risetime, dV/dt, of these silicon-based solid-state diodes remain on the order of 1012 V/s. Furthermore, all possible ways to improve pulse performance of DSRD made by deep diffusion have been extensively investigated and exhausted. To achieve the 1013 V/s (10 kV/ns) voltage-to-risetime required by an all-solid-state pulse generation utilized to support of the missions, improving DSRD manufacturing techniques must ensue.The process flow is schematically illustrated by Fig. 1. On starting degenerate doped wafer, two epitaxial layers are grown, first n- then p-type doped thus forming p-n junction of the diode.The doping profile is controlled by changing dopant flow into epi chamber. It allows getting an optimal diode doping profile predicted by simulation. Notice, the old diffusion process allows only predetermined doping profile (complementary error function) which is not optimal.After forming the blanket p-n junction structure on entire wafers, individual diode dies are separated by wafer patterning. Though the wafers remain intact. This is opposite to the old process where the wafers were cut into individual diode dies. In our technology, V-grooves are formed by anisotropic etching process resulting in structure shown on Fig. 2. Squares surrounded by the v-grooves will become diodes, Inner slopes of v-grooves become side walls of the diodes. Notice, in old technology side walls were usually vertical, which creates a weak point for electrical breakdown: it is limited by surfacee breakdown properties, not bulk silicon properties.Next is diode side surface insulation. It is achieved by thermal oxidation. Thus, the diodes get the best surface passivation (i.e., thermal SiO2). The p-n junction is located near middle of the V-groove slope. Thus, there is no local spike of electric field where avalanche breakdown starts. Eventually, the breakdown properties of this diode are much closer to bulk silicon limit – as compared to old technology where the breakdown was surface limited.At next stage the silicon dioxide layer is removed on top surface but remains on v-groove slopes. Now we have wafers with diode arrays, terminated and passivated by side surfaces.Further, selective electroplating of copper is performed to form electrical contacts. Also, it is a step in preparation to wafer stacking. In old technology, metallization was at much earlier stage of flow and thus it interfered with side insulation. In selective electroplating, copper is deposited only on silicon surfaces, and does not deposit on SiO2 surfaces of v-groove insulation.To finish preparation for wafer bonding, tin is selectively deposited over copper. Then, wafers are aligned and stacked. The wafer stack is heated above tin melting temperature. By solid-liquid interdiffusion, Cu/Sn intermetallic compound is formed. It has much higher melting point compared to tin. Bonding process continues until entire tin layer is consumed.Now the bonded wafer stack is ready for last step in the processing – cutting into stacked DSRDs. The cutting is regular mechanical sawing. The saw lines are along the lines of v-grove bottoms.The process and resulting device design are patented [4].On next step of this project, electrical performance of final stacked DSRDs will be compared to performance of stacked DSRDs manufactured by traditional deep diffusion-based technology. Boff, A., J. Moll, and R. Shen. "A new high-speed effect in solid-state diodes." in 1960 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, vol. 3, pp. 50-51. IEEE, 1960. Grekhov, I. V., V. M. Efanov, A. F. Kardo-Sysoev, and S. V. Shenderey. "Power drift step recovery diodes (DSRD)." Solid-State Electronics 28, no. 6 (1985): 597-599..Rukin, S. N. "Pulsed power technology based on semiconductor opening switches: A review." Review of Scientific Instruments 91, no. 1 (2020): 011501.Bellinger, A.Caruso, A.Usenko, US Patent Application “Stacked Diode with Side Passivation and Method of Making the Same” filed 09/10/2021. Figure 1

Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC)

This Special Issue of the IEEE Journal of Solid-State Circuits is dedicated to a collection of the best articles selected from the 2020 IEEE International Solid-State Circuits Conference (ISSCC) that took place on February 16–20, 2020, in San Francisco, CA, USA. This Special Issue covers articles from the Wireline, Digital Circuits, Digital Architectures and Systems (DASs), Machine Learning and AI, and Memory Committees.

Guest Editorial: Selected Papers From the 2020 IEEE International Solid-State Circuits Conference

The eight papers in this special section were presented at the IEEE International Solid-State Circuits Conference (ISSCC)that was held in San Francisco, California, from February 16 to February 20, 2020.

Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC)

This Special Issue of the IEEE Journal of Solid-State Circuits is dedicated to a collection of the best papers selected from the 2020 IEEE International Solid-State Circuits Conference (ISSCC) that took place on February 16–20, 2020, in San Francisco, CA, USA. This issue covers papers from the Analog, Power Management, Data Converters, RF, and Wireless committees.

Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC)

It is an annual tradition ever from the start of the IEEE Journal of Solid-State Circuits (JSSC) in 1966 to publish extended manuscripts of a selected set of papers presented at the annual International Solid-State Circuits Conference (ISSCC). In this November issue, you will find selected papers from the Imagers, Medical, MEMS, and Displays (IMMD) and the Technology Directions (TD) sessions. Most of the bio-related papers are covered in these topics. Next month, the sessions of Analog, Power Management, Data Converters, RF, and Wireless will be covered, and in January, you will find the selected papers from the Wireline, Digital Circuits, Digital Architectures and Systems, Memory, and Machine Learning subcommittees.

Combined Power Ratio Calculation, Hadamard Transform and Least Mean Squares Algorithm for Channel Mismatch Calibration in Time-Interleaved ADCs

This paper presents a method for all-digital background calibration of multiple channel mismatches including offset, gain and timing mismatches in time-interleaved analog-to-digital converters (TIADCs). The average technique is used to remove offset mismatch at each channel. The gain mismatch is calibrated by calculating the power ratio of the sub-ADC over the reference ADC. The timing skew mismatch is calibrated by using Hadamard transform for error correction and LMS for timing mismatch estimation. The performance improvement of TIADCs employing these techniques is demonstrated through numerical simulations. Besides, achievement results on the field-programmable gate array (FPGA) hardware have demonstrated the effectiveness of the proposed techniques.
 KeywordsTime-interleaved analog-to-digital converter (TIADC), channel mismatches, all-digital background calibration
 References[1] Melamed and S. Toledo, A robust, selective, and flexible RF front-end for wideband sampling receivers, ICT Express 3(2) (2017) 96-100.[2] C. Black and D. A. Hodges, Time interleaved converter arrays, IEEE Journal of Solid-state circuits 15(6) (1980) 1022-1029.[3] Razavi, Design considerations for interleaved ADCs, IEEE Journal of Solid-State Circuits 48(8) (2013) 1806-1817.[4] Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, and K. Kobayashi, Explicit analysis of channel mismatch effects in time-interleaved ADC systems, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 48(3) (2001) 261-271.[5] Vogel, The impact of combined channel mismatch effects in time-interleaved ADCs, IEEE transactions on instrumentation and measurement 54(1) (2005) 415-427.[6] J. Harpe, J. A. Hegt, and A. H. van Roermund, Analog calibration of channel mismatches in time‐interleaved ADCs, International Journal of Circuit Theory and Applications 37(2) (2009) 301-318.[7] Camarero, K. B. Kalaia, J.-F. Naviner, and P. Loumeau, Mixed-signal clock-skew calibration technique for time-interleaved ADCs, IEEE Transactions on Circuits and Systems I: Regular Papers 55(11) (2008) 3676-3687. DOI: 10.1109/TCSI.2008.926314.[8] Le Duc, D. M. Nguyen, C. Jabbour, T. Graba, P. Desgreys, and O. Jamin, All-digital calibration of timing skews for TIADCs using the polyphase decomposition, IEEE Transactions on Circuits and Systems II: Express Briefs 63(1) (2015) 99-103.[9] Le Duc, D. M. Nguyen, C. Jabbour, T. Graba, P. Desgreys, and O. Jamin, Hardware implementation of all digital calibration for undersampling TIADCs, in 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, pp. 2181-2184.[10] Guo, S. Tian, and Z. Wang, Estimation and correction of gain mismatch and timing error in time-interleaved ADCs based on DFT, Metrology and Measurement Systems 21(3) (2014) 535-544.[11] Qiu, Y.-J. Liu, J. Zhou, G. Zhang, D. Chen, and N. Du, All-digital blind background calibration technique for any channel time-interleaved ADC, IEEE Transactions on Circuits and Systems I: Regular Papers 65(8) (2018) 2503-2514.[12] Matsuno, T. Yamaji, M. Furuta, and T. Itakura, All-digital background calibration technique for time-interleaved ADC using pseudo aliasing signal, IEEE Transactions on Circuits and Systems I: Regular Papers 60(5) (2013) 1113-1121.[13] Saleem and C. Vogel, On blind identification of gain and timing mismatches in time-interleaved analog-to-digital converters, in 33rd International Conference on Telecommunications and Signal Processing, Baden (Austria), 2010, pp. 151-155.[14] W. Kang, H.-K. Hong, S. Park, K.-J. Kim, K.-H. Ahn, and S.-T. Ryu, A sign-equality-based background timing-mismatch calibration algorithm for time-interleaved ADCs, IEEE Transactions on Circuits and Systems II: Express Briefs 63(6) (2016) 518-522.[15] H. Chen, J. Lee, and J.-T. Chen, Digital background calibration for timing mismatch in time-interleaved ADCs, Electronics Letters 42(2) (2006) 74-75.[16] Liu, N. Lv, H. Ma, and A. Zhu, Adaptive semiblind background calibration of timing mismatches in a two-channel time-interleaved analog-to-digital converter, Analog Integrated Circuits and Signal Processing 90(1) (2017) 1-7.[17] Chen, Y. Pan, Y. Yin, and F. Lin, All-digital background calibration technique for timing mismatch of time-interleaved ADCs, Integration 57 (2017) 45-51.[18] Van-Thanh, H. Van-Phuc, and X. Tran, All-Digital Background Calibration Technique for Offset, Gain and Timing Mismatches in Time-Interleaved ADCs, EAI Endorsed Transactions on Industrial Networks and Intelligent Systems 6(21) (2019). DOI: 10.4108/eai.24-10-2019.160983.[19] Le Dortz et al., 22.5 A 1.62 GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70dBFS, in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), IEEE, 2014, pp. 386-388.[2] Tertinek and C. Vogel, Reconstruction of nonuniformly sampled bandlimited signals using a differentiator–multiplier cascade, IEEE Transactions on Circuits and Systems I: Regular Papers 55(8) (2008) 2273-2286.[21] Cho et al., Calibration of channel mismatch in time-interleaved real-time digital oscilloscopes, in 2015 85th Microwave Measurement Conference (ARFTG), IEEE, 2015, pp. 1-5.

Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC)

This Special Issue of the IEEE Journal of Solid-State Circuits is dedicated to a collection of the best articles selected from the 2019 IEEE International Solid-State Circuits Conference (ISSCC) that took place on February 17–21, 2019, in San Francisco, CA, USA. This Special Issue covers articles from the Wireline, Digital Circuits, Digital Architectures and Systems (DASs), and Memory Committees.

Guest Editorial Selected Papers From the 2019 IEEE International Solid-State Circuits Conference

The six papers in this special section were presented at the IEEE International Solid-State Circuits Conference (ISSCC 2019) that was held in San Francisco, California, from February 17 to February 21, 2019.

Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC)

This special Issue of the IEEE Journal of Solid-State Circuits is dedicated to a collection of the best articles selected from the 2019 IEEE International Solid-State Circuits Conference (ISSCC) that took place on February 17–21, 2019, in San Francisco, CA, USA. This issue covers articles from the Analog, Power Management, Data Converters, RF, and Wireless Committees.