IDCT Operations Research Articles

A novel chaotic steganography method with three approaches for color and grayscale images based on FIS and DCT with flexible capacity

In this paper, a new chaotic steganography method based on Fuzzy Inference System (FIS), using Discrete Cosine Transform (DCT) on color and grayscale images is proposed. The proposed algorithm is designed in three different approaches to have important factors of robustness, imperceptibility, and transparency with respect to applications. In order to achieve this goal, important parameters in the Human Visual System (HVS), such as texture and luminance, using DCT coefficients are computed. For more precision and flexibility in selecting host blocks for embedding, FIS system is used. Due to the importance of robustness and transparency in different applications, the best target host blocks are intelligently determined using the degree defined in the fuzzy system. This flexibility greatly enhances the efficiency of the algorithm in various using goals. One of the outstanding aspects of the proposed method is error controlling with increasing capacity. At first, embedding is done on middle frequency (MF) then to increase the capacity, coefficients in high frequency are also considered with two different zigzag scanning directions in selection, middle to high (MHF) and high to middle (HMF). The ordering selection of different color channels (for color image), blocks, coefficients in embedding phase, and encryption algorithm of secret message are done by chaotic sequences which has a positive impact on security level. Providing an efficient integration technique (synchronization) in the number of coefficients of each block leads to increasing the security of the proposed method. One of best novelty which causes decreasing bit error rate (BER) beside increasing capacity, is approximating of the distortion during DCT and IDCT operations in embedding phase. The experimental results demonstrate that high level of transparency and robustness for MF, and if more capacity is needed, although both algorithms HMF and MHF have desirable results, but HMF provides higher level of transparency and MHF more robustness against noises and attacks which can be used with respect to applications.

A Fast Inverse Motion Compensation Algorithm for DCT-Domain Video Transcoder

The existing methods to perform motion compensation (MC) in discrete cosine transform (DCT) treat each 8 times 8 block as a fundamental unit and, therefore, involve the high cost of reconstructing prediction frames, especially when the half-pixel motion vectors (MVs) are involved. The proposed method operates on a block of variable size 16 Ny times 16 Nx, where Nx and Ny are the number of adjoining 16 times 16 macroblocks with common MV, along the horizontal and vertical directions, respectively. We demonstrate that a basic operation in reconstructing an 16 Ny times 16 Nx DCT-MC block, both with integer and half-pixel MV, can be represented as a multiplication by fixed matrices, and the computations can be greatly simplified through decomposition of DCT/ IDCT operations. Experimental results using cascaded DCT domain transcoder show substantial reduction in computations at quality close to pixel domain transcoding.

IEEE-Compliant IDCT on FPGA-Augmented TriMedia

This paper presents a TriMedia processor extended with an IDCT reconfigurable design, and assesses the performance gain such an extension has when performing MPEG-2 decoding. We first propose the skeleton of an extension of the TriMedia architecture, which consists of a Field-Programmable Gate Array (FPGA)-based Reconfigurable Functional Unit (RFU), a Configuration Unit managing the reconfiguration of the RFU, and their associated instructions. Then, we address the computation of the 8 × 8 (2-D) IDCT on such extended TriMedia and propose a scheme to implement the 1-D IDCT operation on the RFU. When mapped on an ACEX EP1K100 FPGA from Altera, the proposed 1-D IDCT exhibits a latency of 16 and a recovery of 2 TriMedia@200 MHz cycles, and occupies 45% of the logic cells of the device. By configuring the 1-D IDCT on the RFU at application launch-time, the IEEE-compliant 2-D IDCT can be computed with the throughput of 1/32 IDCT/cycle. This figure translates to an improvement over the standard TriMedia of more than 40% in terms of computing time when 2-D IDCT is carried out in the framework of MPEG-2 decoding. Finally, the proposed reconfigurable IDCT is compared to a number of existing designs.