IC Solutions Research Articles

Hybrid Monolithic 3-D IC Floorplanner

With continued technology scaling, interconnects have become the bottleneck in further performance and power consumption improvements in modern microprocessors. 3-D integrated circuits (3-D ICs) provide a promising approach for alleviating this bottleneck and enabling higher performance while reducing the footprint area, wirelength, and overall power consumption. Among various 3-D IC solutions, monolithic 3-D ICs stand out as they can utilize the third dimension most efficiently owing to high-density monolithic intertier vias. Monolithic integration is possible at different levels of granularity: block level, gate level, and transistor level. A hybrid monolithic design has modules implemented in different monolithic styles to further optimize the design objectives such as area, wirelength, and power consumption. However, a lack of electronic design automation tools makes the hybrid monolithic 3-D IC design quite challenging. In this paper, we introduce the first hybrid monolithic 3-D IC floorplanner. We characterize the OpenSPARC T2 processor core using different monolithic implementations and compare their footprint area, wirelength, power consumption, and temperature. We show, via simulations, that under the same timing constraint, a hybrid monolithic design offers 48.1% reduction in the footprint area and 14.6% reduction in power consumption compared to those of the 2-D design at the cost of higher power density and slightly higher temperature.

Corporate control and ownership networks

In this paper, authors consider ownership networks to quantify the ease with which a company can be controlled due to the shareholding relationships in which it is involved. These networks have been usually considered in a descriptive perspective, either to quantify the control exerted by an ultimate shareholder, especially in presence of complex patterns of indirect control, or as a subject of topological analysis. Recently, a new stream of literature arose, solving optimization problems on ownership networks. Among these tools, authors explicitly refer to the Indirect Control Problem (IC) (Martins & Neves, 2017), which determines the minimum cost control strategy of a set of Target company, namely a strategy to build a robust investment fund which includes the corporate control on one or more companies. In this paper, we combine the descriptive and the optimization approach, introducing a linear programming model, namely Cheapest Control Problem (CCP), contributing on both the descriptive and the optimization approach. In particular, authors propose CCP overcome some of the IC main limitations, i.e. the overestimation of control in presence of mutual cross-shareholdings. Furthermore, CCP solutions allow computing three indexes that measure the ease with which a company can be controlled depending on its ownership relationships. Finally, a case study is incorporated to compare IC and CCP solutions, discussing the informative power of the indices introduced.

Fan-Out Wafer-Level-Packaging: Market and Technology Trends

Abstract The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D investments in new lithography solutions and devices below 10nm nodes are rising substantially. In order to answer market demands, the industry seeks further performance and functionality boosts in integration. While scaling options remain uncertain in the shorter term and continue to be investigated, the spotlight turns to advanced packages. Emerging packages such as fan-out wafer level packages and 2.5D/3D IC solutions together with more conventional but upgraded flip chip BGAs aim to bridge the gap and revive the cost/performance curve while at the same time adding more functionality through integration. Embedded packages are nowadays not anymore just an interesting approach for specific applications. Benefiting from 3D TSV high cost, these packages could fit the high expectations of the industry. Indeed, added value of embedded packages in terms of integration, reliability and even cost at system level is already clear for manufacturers. Embedded packages lacked success until 2013–2014 because of long time of qualification, few players involved and customer convincing time. The situation changed with new product announcements and strong involvement of some key players, lately most notably TSMC. In this work we will focus on one main type of embedded package of most interest at the moment: Fan-Out wafer level package. The principle of Fan-Out technology is to embed products in a mold compound and allow redistribution layer pitch to be independent from die size. This approach is already mature enough to have high volume products claimed by Nanium and JCET/Stats ChipPAC using eWLB type of Fan-Out, with many other developments from OSATs and an aggressive technology from TSMC (inFO). The market for Fan-Out packages in 2015 almost reached $500M, with potential breakthrough events in store in 2016 that could triple the 2015 market and continue further with more than 30% growth. Understanding the potential of that market and the high demand from telecom industry for a thin and cheap package, other important OSATs like Powertech or Amkor are willing to enter the market with their own technologies. TSMC is also proposing its inFO process to its customers, confirming that foundries could look at the OSATs reserved market through wafer-level packages. Each player has its own view on how to gain market share and meet the challenges such as cost reduction, panel manufacturing, yield improvement, die shift… The presentation will provide an overview of the products announcements, commercialization roadmaps as well as market forecasts per application. Insights and trends into the different fan-out packaging approaches by applications, business models and major players will be reviewed.

2.5D / 3D IC Landscape: Market and Technology Trends

The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D investments in new lithography solutions and devices below 10nm nodes are rising substantially. In order to answer market demands, the industry seeks further performance and functionality boosts in integration. While scaling options remain uncertain and continue to be investigated, the spotlight is turning to advanced packages. Emerging packages such as fan-out wafer level packages and 2.5D / 3D IC solutions together with upgraded flip chip BGAs aim to revive the cost/performance curve and extend both scaling and functionality roadmaps. Future packages need to tackle the explosion in information exchange translating to high number of I/Os and be able to support heterogeneous integration. This puts particular pressure on die to board interconnects. Technologies to fill the void created in diverging PCB versus IC feature sizes are constantly under development. Three-dimensional (3D) technology using the well-known Through Silicon Via (TSV) interconnect, considered today the most advanced technology, is one emerging option that aims to enable heterogeneous integration. Such a technology is not limited to CMOS scaling in itself, it is rather based on bringing more functionality by stacking different type of devices (Logic, Memory, Analog, MEMS, Passive components…) while reducing the package form factor. This functional diversification is also known as More-than-Moore. This work focuses on the analysis of recent developments and future trends of the 2.5D / 3D IC landscape. What's new since last year? TSV technology has already been utilized for several years within the MEMS and CMOS image sensor (CIS) market, but the news is that it finally seems to be happening within the logic and memory domain. Latest products such as AMD Radeon R9 Fury with its 2.5D configuration including HBM stacks and Samsung 3D TSV stacked DRAM, among others, aim for high volume. Fueled by consumer applications such as smartphones and tablets, the MEMS and CIS markets are expected to exhibit continuous growth over the next several years, while in the high-end market, driven by the need for further performance increase, volatile memory and especially DRAM are finally opening the doors of 2.5D / 3D IC commercial adoption. This analysis will cover 2.5D interposer & 3DIC platforms as well as MEMS and CIS TSV packaging. Market forecasts in terms of wafer starts, market revenue, application segments and end-products will be presented. Furthermore, supply chain activities and major player interactions will be analyzed and 3D integration technology roadmaps will be reviewed. In conclusion, this study will aim at providing comprehensive insight into 2.5D / 3D IC market and technology trends.

Current thresholds for zero-field steps in long Josephson junctions

Recent compute r s imula t ion studies of the resonant propagat ion of fluxons in long Josephson tunnel junct ions hav ing loss, bias and open-circui t boundary condi t ions (1,2) have demons t ra t ed the existence of bo th upper and lower bias current thresholds for these modes of propagat ion wi th 0 1. The purpose of this note is to point out t ha t analyt ic solutions for resonant fluxon propagat ion in junct ions wi thou t loss or bias, bu t wi th open-eirctfi t bounda ry condit ions (4), imp ly (indirectly) the existence of a lower current threshold 7 ~ > 0. They do not, however , place any l imit on 7 .. . . . Tllus, i t seems to be the ease tha t the existence of 7m~ depends upon the open-circui t boundary condit ions and tha t of 7,n~ upon the loss-bias in teract ion, whereas the precise values for the two thresholds depend upon a combina t ion of both factors.

Extremum principles for a nonlinear kirkwood integral equation

.ho(t) = t ~ 1, It] 1 . Here g(r) is the radia l d is t r ibut ion funct ion which is a nonnegat ive even funct ion of r and is such tha t (4) g(r)-> 1 as r -~ ~ . Numer ica l solutions of this k ind of equa t ion have been obta ined by KIRKWOOD, MAUN and ALD]~R (1). In this paper complenwnta ry var ia t iona l principles for in tegra l equat ions (2,a) are used to find approx ima te analyt ic solutions for equat ions of tile form (1).

Preparation of 7-hydroxy derivatives of thionaphthene. New route for the synthesis of the thionaphthene system

We have found that thieno[2, 3 -c ]pyry] ium sa l t s , which a r e r e a d i l y obtained by the acyla t ion of f i -ace tonyl th iophene [1,2] , undergo c leavage of the py ry l ium r ing under the ac t ion of a lka l i s , and the 3 ace tony l -2 acyl th iophenes so fo rmed then r e e y c l i z e with the fo rma t ion of 7-hydroxy de r iva t i ve s of thionaphthene: .sAc.o fiJ'J2 R 0 The r eac t i on is c a r r i e d out by heat ing aqueous ethanol ic solut ions of th ienopyry l ium sa l t s with an excess of caus t ic soda. In this way we have obtained 7 -hydroxy-5-methy l th ionaphthene (rap 68 ~ C) and 7 h y d r o x y 5 , 6 dimethyl thionaphthene (mp 99-100 ~ C), the s t r u c t u r e of which was shown by IR and NMR spec t roscopy . R E F E R E N C E S 1. G. N. Dorofeenko, L. V. Dulenko, V. I. Dulenko, and S. V. Krivun, ZhORKh, 1, 1171, 1965. 2. S. V. Krivun, L. V. Dulenko, V. I. Dulenko, and G. N. Dorofeenko, DAN, 166, 359, 1966. 26 August 1969 Donetsk Depa r tmen t of Phys i ca l and Organic Chemis t ry , Ins t i tu te of Phys ica l C h e m i s t r y AS UKrSSR

Modern Techniques Used in Nuclear Design of Reactors

has made a profound change in the philosophy and methodology of reactor phys ics and analys is. For example, the role of the reactor physicist has change d cons iderably in the last decade. In the early history of development of reactor physics, much of the attention of the reactor physicist was directed toward analytic solutions of the equations describing the behavior of the neutrons in tractable idealized systems. In order to obtain analyt ic soluti ons, it was necessary to ignore some of the more subtle effects and to introduce approximatio ns both in energy and geomet ric details. These expedients were usually justified because accurate differential cross-section data were not avail able to allow more careful de­ tail. The early reactor physics calcu lational models were usually based on one- or two-group age-diffusion the ory. The parameters used in these calcu­ lations were usually obtained from correlations of integral experiments with simple physical models. In 1950, mult igroup methods were already begin ning to be used (1), particularly for intermediate-ene rgy and fast-spectrum reactors, where the simp lified models were not even approximately valid. The se probl ems, which used as many as 15 energy groups and a sph erical geometry, were solved by iterative procedures with the use of a desk calcu­ lator. The solution of a single problem typically required several days of calculation. However, the method all owed the reactor phys icist to calculate diffusio n, absorpti on, and fission events wit h proper attent ion given to the neutron flux inten sities and cross-section values appropriate to different energy groups and at different radial positions in the reactor.