IC Compiler Research Articles

Efficient architecture for ocular artifacts removal from EEG: A Novel approach based on DWT-LMM

Medical practitioners use portable electroencephalogram (EEG) headset to identify Neuro Developmental Disorders (NDD). However, the analysis of EEG signals gets affected as the recorded electrical activity always contaminated with artifacts. A portable EEG headset requires area-efficient hardware and an effective method to remove ocular artifacts. In this paper, a method is proposed, which removes ocular artifacts efficiently and consumes less hardware. This proposed method involves determining the appropriate decomposition level to obtain approximation coefficients (ACs) and detail coefficients (DCs) for minimal loss of useful information present in the EEG signal. In addition, an algorithm is also proposed to perform wavelet thresholding on wavelet coefficients using Local Maximal and Minimal (LMM) to remove artifacts from EEG signals without disturbing the information related to brain activity. The functionality of the proposed method is verified using MATLAB R2021a tool by computing average correlation coefficient & RMSE performance metrics and the proposed method is also modeled using Verilog HDL. The results show that the proposed DWT-LMM approach had superior performance in removing artifacts from EEG signals with the average correlation coefficient and RMSE values of 0.9369 and 2.2252, respectively. The functionality of this HDL netlist is verified by the VCS simulator and synthesized by Synopsys design compiler 32 nm UMC library cells. The proposed architecture layout is generated after placement & routing using Synopsys IC Compiler tool by employing 32 nm cell libraries and the results shows that the layout consumes 6490.07 μm2 of area and 792.18 μw of power with supply voltage of 0.95 V. Hence, the proposed ocular artifacts removal method and architecture can be employed in portable/wearable brain-computer interface (BCI) devices.

Design of VLSI Based Power-Saving Streetlight System and Automatic Traffic Controller with Automatic Transfer Switch

The number of road accidents is increasing due to the power outage of the traffic light system and the streetlight system's maintenance fees was too high. Therefore, a proposed solution that includes automatic traffic light controller, energy-saving streetlight controller and automatic energy transfer switch had been designed to overcome these issues. The proposed traffic light is on a four-way junction which has one sensor for each direction. This traffic light controller has 3 different conditions which will act differently when all directions had detected vehicle, or when vehicle is not detected, or when vehicle is detected in some directions. Apart from this, a streetlight controller is also designed to minimize the power usage and the streetlight will only turn on when vehicle is detected. The proposed solution was designed in Quartus 18 via Verilog Hardware Description Language (HDL) and functional simulation is used to verify the proposed circuit is functioning correctly The Verilog HDL files were input to the Synopsys Design Compiler for logical synthesis and IC Compiler for physical synthesis. After both logical and physical synthesis, the design was then analysed in terms of speed, area, and power consumption through the generate report commands. Besides, the proposed energy-saving streetlight was programmed into Field Programmable Gate Array (FPGA) and connected with AC Dimmer Module and LED bulb to measure the power consumption and the reduction of power consumption of the LED bulb. As for the result, the designed chip had a total area of 392.002199 μm^2, positive critical timing slack of 0.1 ns and power consumption of 0.1196 mW. The streetlight was able to achieve a reduction in power consumption by 77.87%.

A Scalable Fully-Digital Differential Analog Voltage Comparator

This paper presents a scalable Fully-digital differential analog voltage comparator designed in Semi-Conductor Laboratory (SCL) 180[Formula: see text]nm complementary metal-oxide semiconductor technology. The proposed design is based on a digital design approach and is easily configurable to lower technology nodes. This design methodology makes the circuit less sensitive to process variations and takes fewer design efforts suitable for Systems-on-a-Chips (SOCs) application. The proposed circuit is designed and simulated in Cadence Virtuoso Analog Design Environment at the supply voltage ranging from 1[Formula: see text]V to 1.8[Formula: see text]V. The fully-digital analog voltage comparator has been synthesized using Synopsys Design Vision and auto-placed & auto-routed using Synopsys IC Compiler. This proposed comparator has a resolution of up to 7-bit at a supply voltage of 1.8[Formula: see text]V and a worst-case operating frequency of about 750 MHz at the TT corner. The obtained value of the offset voltage and delay is 0.55[Formula: see text]mV and 0.72 ns, respectively. The simulated results have shown that the power dissipation of the proposed scalable analog voltage comparator is [Formula: see text][Formula: see text]V and [Formula: see text][Formula: see text]V supply voltage, respectively. Also, the RC extracted post-layout simulations have been implemented to verify the performance, which does not affect the results much.

Reconfigurable Carry Look-Ahead Adder Trading Accuracy for Energy Efficiency

The modern portable devices exhibiting multimedia applications demand higher energy efficient signal processing due to limited battery size. The approximate adders have shown a remarkable energy-efficiency over the accurate adders for error tolerant applications. In this paper, three novel approximate carry look-ahead adder (ACLA) architectures are proposed. These approximate ACLAs are achieved by simplifying the Boolean expression of carry generation logic such that the probability of error is small while eliminating number of logic gates. Further, a novel accuracy reconfigurable CLA (Re-CLA) that provides desired quality/accuracy in the given energy budget is proposed. The post layout synthesis results using Synopsys IC Compiler of the proposed adders are computed and analysed against the existing adders. These results demonstrate 37.67%, 18.21%, 18.14% and 15.92% reduction in energy consumption by the proposed 8-bit ACLA-I, -II, -III and -IV adders respectively over the existing approximate adder. Further, the proposed 8-bit and 16-bit Re-CLAs require only 1.92% and 7.08% more energy over the existing CLA for achieving accuracy reconfigurability. Finally, the synthesis results of the Gaussian smoothing filters embedded with the proposed adders show higher energy efficiency with acceptable image quality over the state-of-the-art adder architectures.

EMSpice: Physics-Based Electromigration Check Using Coupled Electronic and Stress Simulation

In this article, a novel full-chip EM simulation tool, called EMSpice simulator is proposed. The new method starts from first principles and simultaneously considers two major interplaying physics effects in EM failure process: the hydrostatic stress and electronic current/voltage in a power grid network. The new tool starts by reading the power grid layout information from Synopsys IC Compiler. It then removes immortal interconnect wires by considering both nucleation phase immortality and incubation phase immortality for multi-segment interconnects. Thereafter, a finite difference time domain (FDTD) solver is employed for stress analysis for every mortal interconnect tree for both nucleation and post-voiding phases. At the whole power grid circuit level, the EM analysis is coupled with IR drop analysis of a whole power grid network at each time step so that we can consider the interaction among stress, void growth, resistance change and IR drop in a single simulation framework. Accuracy of EMSpice is validated by comparing with a published EM simulator, XSim, for nucleation phase, and finite element method based COMSOL for post-voiding phase. The comparison results show that EMSpice agrees well with both methods with. Experimental results on two practical processor chip designs show that the proposed coupled EM-IR drop analysis method can further reduce the overly conservative EM-aware power grid design as the number of the failed trees found by EMSpice simulator is up to 76.7% less than the Black's method and 66.7% less than a recently proposed full-chip EM analysis method respectively. Furthermore EMSpice simulator is the least conservative one for lifetime estimation of individual tree wires among the three methods.

Power efficient synchronous counter design

The Performance of any VLSI circuit depends on its design architecture, which optimizes power and provides high reliability. To design any circuit with low power, power optimization of circuit at different levels is needed. Most of the system level architectures consists of sequential circuits, design of these circuits plays an pivotal role in reducing overall power of the system. Counters are basic building blocks in many VLSI applications such as timers, memories, ADCs/DACs, frequency dividers etc. It is observed that design of counters has power overhead because of requirement of high power consumption for the clock signal distribution and undesired activity of flip-flops due to presence of clocks. In this brief, we propose a power efficient design of synchronous counters that reduces the power consumption due to clock distribution for different flip-flops and offers high reliability. The proposed counter design is evaluated and analyzed in terms of power in a standard 45 nm CMOS technology in CADENCE and also evaluated in Synopsys Design Compiler and IC Compiler for ASIC (Application Specific Integrated Circuit) synthesis results. The proposed counter design has lower power requirement and power-area product than existing counter architectures and the power reduction is more significant for wide-bit counters.

Performance analysis of Horner's rule-based canonical signed digit lifting architecture for two-dimensional discrete wavelet transform

The high performance of image compression is needed greater as digital image finds its way into many areas of everyday life. JPEG 2000 is one of the best image compression standards in which DWT (Discrete Wavelet Transform) is used. In this paper, an efficient two-dimensional (2D) DWT 9/7 and 6/10 filter based on Horner's Rule with Canonical Signed Digit is proposed. Canonical Signed Digit is based on the positional values of 1's in the representation, whereas Horner's rule-based Canonical Signed Digit is based on the distance between the positions of 1's. Implementing the Canonical Signed Digit and Horner's Rule with Canonical Signed Digit architectures of 9/7 and 6/10 filters in Synopsys IC Compiler with 90 nm technology shows the reduction of 31.07% and 36.86% in the total dynamic power along with reduction of 25.72% and 31.17% in the total area, respectively, when compared with the existing method.

Effective Power Optimization Under Timing and Voltage-Island Constraints Via Simultaneous $V_{dd}$, $V_{th}$ Assignments, Gate Sizing, and Placement

We present a physical-synthesis based power optimization technique that simultaneously explores the four transforms, multiple Vdd, multiple Vth , cell sizing, and placement, to find a minimum power solution under timing and other constraints. The optimal selection of the design options of all transforms for all cells in the circuit is solved using a new optimization technique called discretized network flow that we have recently developed. Among the constraints we consider, timing and the voltage-island constraints are the two most important and complex ones. The voltage-island constraint specifies the maximum allowed number of voltage islands in the layout, and the requirement that each island be rectangular. We develop an approach that along with the option selection process can simultaneously determine the voltage islands needed, as well as satisfy all given constraints. Experimental results on ISCAS'89 and Faraday benchmarks show that compared to an initial wire length (WL)-optimized placement with high supply and low threshold voltage levels, we obtain a power reduction by up to 42% and an average of 30% for the same delay as that of the initial design. These improvements are also 44-50% relatively better than the improvements yielded by sequentially applying the four power reduction transforms, which is the currently standard method for applying multiple transforms. Finally, compared to an industry tool Synopsys IC Compiler (ICC) that also applies all four transforms, our method reduces power by an additional amount of up to 19%, and an average of 16%.