IBM Cell Broadband Engine Research Articles

Analysis of Parallel Multidimensional Wave Digital Filtering Network on IBM Cell Broadband Engine

As an alternative approach for the numerical integration of physical systems, the MDWDF technique has become of importance in the field of numerical analysis due to its attractive features, for example, massive parallelism and high accuracy both inherent in nature. In this study, speed-up efficiencies of a MDWDF network are studied for the linearized shallow water system, which plays an important role in fluid dynamics. To achieve the goal, the full parallelism of the MDWDF network is established in the first place based on the chained MD retiming technique. Following the implementation on the IBM Cell Broadband Engine (Cell/BE), excellent performance of the full parallel architecture is revealed. The IBM Cell/BE containing 1 power processor element (PPE) and 8 synergistic processor elements (SPEs) perfectly fits the architecture of the retimed MDWDF model. Empirical results have demonstrated that the full parallelized model with 8 processors (1PPE + 7SPEs) outperforms the other three models: partial right/left-loop retimed models and the full sequential model with 4× improvements for scheduled grids 51×51. In addition, for scheduled fine grids 201×201, the full parallel model is shown to possess significant performance over these models by up to 7× improvements.

Scheduling of synchronous data flow models onto scratchpad memory-based embedded processors

In this article, we propose a heuristic algorithm for scheduling synchronous data flow (SDF) models on scratch pad memory (SPM) enhanced processors with the objective of minimizing its steady-state execution time. The task involves partitioning the limited on-chip SPM for actor code and data buffer, and executing actors in such a manner that the physical SPM is time shared with different actors and buffers (formally defined as code overlay and data overlay, respectively). In our setup, a traditional minimum buffer schedule could result in very high code overlay overhead and therefore may not be optimal. To reduce the number of direct memory access (DMA) transfers, actors need to be grouped into segments. Prefetching of code and data overlay that overlaps DMA transfers with actor executions also need to be exploited. The efficiency of the our heuristic was evaluated by compiling ten stream applications onto one synergistic processing engine (SPE) of an IBM Cell Broadband Engine. We compare the performance results of our heuristic approach with a minimum buffer scheduling approach and a 3-stage ILP approach, and show that our heuristic is able to generate high quality solutions with fast algorithm run time.

Parallel Implementation of the Wideband DOA Algorithm on Single Core, Multicore, Gpu and Ibm Cell be Processor

The Multiple Signal Classification (MUSIC) algorithm is a powerful technique for determining the Direction of Arrival (DOA) of signals impinging on an antenna array.The algorithm is serial based, mathematically intensive, and requires substantial computing power to realize in real-time.Recently, multi-core processors are becoming more prevalent and af-fordable.The challenge of adapting existing serial based algorithms to parallel based algorithms suitable for today’s mul-ti-core processors is daunting. DOA algorithm has been implemented on Multicore (Intel Nehalem Quad Core), NVIDIA’s GPU GeForce GTX 260, and IBM Cell Broadband Engine Processor. This is in an effort to use DOA for real time applications. The DOA algorithm has been parallelized, partitioned, mapped, and scheduled on Multi-Core, GPU, and IBM Cell BE processor.The parallel algorithm is developed in C# for Intel Nehalem Quad Core, a combination of C and CUDA for GPU, and C++ for IBM Cell processor. The algorithm has also been implemented on single core for comparison purposes. Wideband DOA algorithm is implemented assuming 16 and 4 sensors using Uniform Linear Array (ULA).

Parallel Implementation of the Irregular Terrain Model (ITM) for Radio Transmission Loss Prediction Using GPU and Cell BE Processors

The Irregular Terrain Model (ITM), also known as the Longley-Rice model, predicts long-range average transmission loss of a radio signal based on atmospheric and geographic conditions. Due to variable terrain effects and constantly changing atmospheric conditions which can dramatically influence radio wave propagation, there is a pressing need for computational resources capable of running hundreds of thousands of transmission loss calculations per second. Multicore processors, like the NVIDIA Graphics Processing Unit (GPU) and IBM Cell Broadband Engine (BE), offer improved performance over mainstream microprocessors for ITM. We study architectural features of the Tesla C870 GPU and Cell BE and evaluate the effectiveness of architecture-specific optimizations and parallelization strategies for ITM on these platforms. We assess the GPU implementations that utilize both global and shared memories along with fine-grained parallelism. We assess the Cell BE implementations that utilize direct memory access, double buffering, and SIMDization. With these optimization strategies, we achieve less than a second of computation time on each platform which is not feasible with a general purpose processor, and we observe that the GPU delivers better performance than Cell BE in terms of total execution time and performance per watt metrics by a factor of 2.3x and 1.6x, respectively.

Library Support in an Actor-Based Parallel Programming Platform

Actor model-based design is actively researched for parallel embedded SW design since the model exposes the potential parallelism explicitly in an architecture-neutral form. In most actor-oriented models, actors are self-contained and data channels are the only sharable object between actors, and they compose a system in a flat layer. In contrast, it is common to use shared library functions and construct vertically layered software for efficiency and modularity. To fill this gap between modeling and implementation, we propose a special actor, library task, with new types of ports: library master port and library slave port. It is a sharable and mappable object that defines a set of function interfaces inside. N:1 master-slave connection allows sharing a library task and the master-slave connection can specify vertically layered software and client-server applications naturally. To support the library task in our embedded software design environment, we develop an automatic mapping algorithm as well as an automatic code generator. The design environment with the library task is applied for two target platforms: IBM CELL Broad band Engine and an ARM-based multicore simulator. Preliminary experiments show that the special actor, or library task, extends the expression power of the previous actor model with efficiently generated codes.

Performance Evaluation of Convolution on the Cell Broadband Engine Processor

Convolution represents a major computational load for many scientific and engineering applications, including seismic surface simulations and seismic imaging. Since convolution presents a heavy computational load, increasing its efficiency can significantly enhance the performance of associated applications. In this work, we present an in-depth analysis of the convolution algorithm and its complexity in order to develop adequate parallel algorithms. The implementation of these algorithms and their evaluation on the IBM Cell Broadband Engine (BE) processor reveals the gains and losses achieved by parallelizing the direct convolution. The performance results show that despite the complexity of the convolution processing, a speedup gain of at least 71.4 is obtained. The parallel vectorized algorithm requires the development effort of considering three independent vectorization strategies. Given the wide availability of Cell processors, the proposed parallelization approach can be widely adopted by any convolution-based application.

Performance, optimization, and fitness: Connecting applications to architectures

Recent trends involving multicore processors and graphical processing units (GPUs) focus on exploiting task- and thread-level parallelism. In this paper, we have analyzed various aspects of the performance of these architectures including NVIDIA GPUs, and multicore processors such as Intel Xeon, AMD Opteron, IBM's Cell Broadband Engine. The case study used in this paper is a biological spiking neural network (SNN), implemented with the Izhikevich, Wilson, Morris–Lecar, and Hodgkin–Huxley neuron models. The four SNN models have varying requirements for communication and computation making them useful for performance analysis of the hardware platforms. We report and analyze the variation of performance with network (problem size) scaling, available optimization techniques and execution configuration. A Fitness performance model, that predicts the suitability of the architecture for accelerating an application, is proposed and verified with the SNN implementation results. The Roofline model, another existing performance model, has also been utilized to determine the hardware bottleneck(s) and attainable peak performance of the architectures. Significant speedups for the four SNN neuron models utilizing these architectures are reported; the maximum speedup of 574x was observed in our GPU implementation. Our results and analysis show that a proper match of architecture with algorithm complexity provides the best performance. Copyright © 2010 John Wiley & Sons, Ltd.

MO-FF-A4-03: A Parallel and Robust Image Registration Algorithm of Consecutive Stained Prostate Specimens for Ultrasound Tissue Characterization of Prostate Cancer

Purpose: To develop a robust and accurate image registration algorithm for the hymatoxylin stained pathology specimens for ultrasoundtissue characterization of prostate cancer.Method and Materials: A landmark based nonlinear image registration algorithm is proposed. It was shown to be effective and robust under conditions of large deformations. In landmark based registration, the most important step is establishing the correspondence among the selected landmark points. This usually requires an extensive search which is often computationally expensive. We introduced a non‐regular data partition algorithm using the K‐means clustering algorithm to group the landmarks based on the number of available processing cores. The step optimizes the memory usage and data transfer. We have tested our method using IBM Cell Broadband Engine platform. Results: This technology was tested and evaluated on hymatoxylin stained pathology specimens for prostate cancer. The tested data sets consisted of ten patients and each patient had more than 3 sets of image slices: 3‐D in vivo and ex vivoultrasoundimages, and 3‐D pathologyimages. The 3‐D ultrasound data had a 2mm step size while the 3‐D pathology step size was 4mm. Successful register was demonstrated with consecutive slices even though they exhibited significant slice cutting induced deformation and tissue missing. The ex vivoultrasoundimages served as a verification of our registration technique. Moreover, the parallel algorithm, which is implemented on IBM cell broad band engine, helps us to achieve 10 fold speed‐up. Conclusion: We have introduced a parallelization of an accurate image registration algorithm. The method is implemented on a IBM Cell/B.E. We have achieved approximately 10 fold speed up compared with its sequential implementation. Our proposed data partitioning approach and the parallelization schema are independent of the parallel platforms and are generic by design, therefore it can be extended to other applications on other parallel platforms.

PFFTC: An improved fast Fourier transform for the IBM cell broadband engine

Abstract The Fast Fourier Transform (FFT) is a widely used algorithm that is frequently employed in environments where high performance is critical. In the context of embedded systems, FFTs often have hard runtime constraints and must be evaluated using limited hardware. In this paper, we present a partitioned FFT algorithm (PFFTC) for the Cell Broadband Engine (Cell BE) that improves upon previous FFT implementations for this platform. PFFTC has three main phases to (i) partition the problem into independent sub-problems, (ii) solve the sub-problems in parallel, and (iii) combine the results of the sub-problems to obtain the solution to the original problem. PFFTC includes optimizations for exploiting data transfer parallelism, avoiding unnecessary communication through careful data routing, avoiding data dependency stalls with instruction-level double buffering, and minimizing synchronization overhead through the use of an “synchronous” signal-based barrier. We evaluate the performance of PFFTC and other FFT algorithms for the Cell BE. Our results indicate that PFFTC attains a peak processing rate of 33.6 GFLOPS, and achieves speedups ranging from 31% to 62% over the fastest previous Cell BE FFT algorithm’s reported performance for complex single-precision FFTs with 1,024-16,384 data points.

Towards high performance computing for molecular structure prediction using IBM Cell Broadband Engine - an implementation perspective

BackgroundRNA structure prediction problem is a computationally complex task, especially with pseudo-knots. The problem is well-studied in existing literature and predominantly uses highly coupled Dynamic Programming (DP) solutions. The problem scale and complexity become embarrassingly humungous to handle as sequence size increases. This makes the case for parallelization. Parallelization can be achieved by way of networked platforms (clusters, grids, etc) as well as using modern day multi-core chips.MethodsIn this paper, we exploit the parallelism capabilities of the IBM Cell Broadband Engine to parallelize an existing Dynamic Programming (DP) algorithm for RNA secondary structure prediction. We design three different implementation strategies that exploit the inherent data, code and/or hybrid parallelism, referred to as C-Par, D-Par and H-Par, and analyze their performances. Our approach attempts to introduce parallelism in critical sections of the algorithm. We ran our experiments on SONY Play Station 3 (PS3), which is based on the IBM Cell chip.ResultsOur results suggest that introducing parallelism in DP algorithm allows it to easily handle longer sequences which otherwise would consume a large amount of time in single core computers. The results further demonstrate the speed-up gain achieved in exploiting the inherent parallelism in the problem and also elicits the advantages of using multi-core platforms towards designing more sophisticated methodologies for handling a fairly long sequence of RNA.ConclusionThe speed-up performance reported here is promising, especially when sequence length is long. To the best of our literature survey, the work reported in this paper is probably the first-of-its-kind to utilize the IBM Cell Broadband Engine (a heterogeneous multi-core chip) to implement a DP. The results also encourage using multi-core platforms towards designing more sophisticated methodologies for handling a fairly long sequence of RNA to predict its secondary structure.

Signal processing on platforms with multiple cores: Part 1 - Overview and methodologies [From the Guest Editors

Multicore processors are now prevalent in all major domains of signal processing. Many laptop and desktop computers today are shipped with dualcore and even quad-core processors. The number of cores is even higher for the Sony PlayStation 3, which is equipped with an 8-core IBM CELL Broadband Engine processor, Nvidia GeForce 9800 GX2, which has 256 stream processors, and SUN UltraSPARC T1/T2 processor, which has 8 cores. Technology predictions indicate that this trend will continue and that the number of cores per processor can easily double around every two or three years.

Special Issue: Exploring the Frontiers of Computing Science and Technology: Adapting Emerging Multi‐ and Many‐core Processors

Recent trends in computer microprocessor development have shifted from a single powerful core to multi- and many-cores. As a result, the continuous improvement in computing power fueled by the exponentially increasing speed of a single processor could be over. With applications such as Earth and space sciences, higher resolutions and more sophisticated treatments of physical processes make models even more computationally intensive. Moreover, the drastic increase of data collected by various instruments requires a significant increase in computing power for data processing and analysis. Therefore, it is crucial for the computational science and technology community to evaluate the impacts of this shift on computationally intensive modeling and data processing applications and to develop appropriate solutions. It is known that the computing power of conventional processors is limited by memory bandwidth. Adding more cores to the processors worsens the problem. It is necessary to adapt computing algorithms to effectively utilize the computing power of those conventional multi- and many-core processors. In the last two years, there have emerged few unconventional processors: IBM's Cell Broadband Engine (hereafter referred to as Cell) and NVIDIA's Graphics Processing Unit (GPU). Intel and AMD are also developing competing Cell- or GPU-like processors, in addition to conventional multi- and many-core processors. It has been demonstrated that certain computationally intensive applications with moderate data communication can benefit from both Cell and GPU with a significant performance improvement. However, these emerging processors require new programming paradigms, which increase the porting costs and impede their effective utilization. To address such issues with the unconventional multi- and many-core processors, this special issue assembles some of the latest research on assessing the impacts of multi- and many-core processors, developing appropriate solutions, and taking advantage of the abundant computing power. The invited papers in this special issue represent augmented works originally presented at the Frontiers of Multicore Computing Conference 2008, held at the University of Maryland, Baltimore County in August 2008. Of course, it is not possible for a single issue to include all the topics addressed by the conference. However, the selected papers cover representative research addressing the issues above. There are four and two papers addressing the issues related to Cell and multi-core processors, respectively. The paper by Germann et al. presents their approaches and optimization methods in porting a short-range parallel molecular dynamics code to the first petaflops computer, Roadrunner, which uses Cells as accelerators 1. The paper by Woodward et al. reports their initial experience with porting and optimizing gas dynamics simulation on Roadrunner 2. The paper by Zhou et al. presents a study on the impact of Cell on the programming paradigm for climate and weather models 3. The paper by Brown et al. presents a contemporary artwork, the ‘Scalable City,’ accelerated with Cell 4. The paper by Wang and JaJa presents a study on interactive direct volume rendering with Intel Clovertown quad-core processors 5. The paper by Simmon and McGalliard provides benchmark results for a variety of high-performance computing applications on the Cray XT3 and XT4, which use dual- and quad-core AMD Opteron processors, and discusses and analyzes multi-core effects 6. The guest editors of this special issue would like to express their deep gratitude to all authors, external reviewers, and Geoffrey Fox for their efforts in making this issue possible.

A Parallel Point Matching Algorithm for Landmark Based Image Registration Using Multicore Platform.

Point matching is crucial for many computer vision applications. Establishing the correspondence between a large number of data points is a computationally intensive process. Some point matching related applications, such as medical image registration, require real time or near real time performance if applied to critical clinical applications like image assisted surgery. In this paper, we report a new multicore platform based parallel algorithm for fast point matching in the context of landmark based medical image registration. We introduced a non-regular data partition algorithm which utilizes the K-means clustering algorithm to group the landmarks based on the number of available processing cores, which optimize the memory usage and data transfer. We have tested our method using the IBM Cell Broadband Engine (Cell/B.E.) platform. The results demonstrated a significant speed up over its sequential implementation. The proposed data partition and parallelization algorithm, though tested only on one multicore platform, is generic by its design. Therefore the parallel algorithm can be extended to other computing platforms, as well as other point matching related applications.

Implementation and Performance Modeling of Deterministic Particle Transport (Sweep3D) on the IBM Cell/B.E.

The IBM Cell Broadband Engine (BE) is a novel multi-core chip with the potential for the demanding floating point performance that is required for high-fidelity scientific simulations. However, data movement within the chip can be a major challenge to realizing the benefits of the peak floating point rates. In this paper, we present the results of implementing Sweep3D on the Cell/B.E. using an intra-chip message passing model that minimizes data movement. We compare the advantages/disadvantages of this programming model with a previous implementation using a master–worker threading strategy. We apply a previously validated micro-architecture performance model for the application executing on the Cell/B.E. (based on our previous work in Monte Carlo performance models), that predicts overall CPI (cycles per instruction), and gives a detailed breakdown of processor stalls. Finally, we use the micro-architecture model to assess the performance of future design parameters for the Cell/B.E. micro-architecture. The methodologies and results have broader implications that extend to multi-core architectures.

Computing discrete transforms on the Cell Broadband Engine

Discrete transforms are of primary importance and fundamental kernels in many computationally intensive scientific applications. In this paper, we investigate the performance of two such algorithms; Fast Fourier Transform (FFT) and Discrete Wavelet Transform (DWT), on the Sony–Toshiba–IBM Cell Broadband Engine (Cell/B.E.), a heterogeneous multicore chip architected for intensive gaming applications and high performance computing. We design an efficient parallel implementation of Fast Fourier Transform (FFT) to fully exploit the architectural features of the Cell/B.E. Our FFT algorithm uses an iterative out-of-place approach and for 1K to 16K complex input samples outperforms all other parallel implementations of FFT on the Cell/B.E. including FFTW. Our FFT implementation obtains a single-precision performance of 18.6 GFLOP/s on the Cell/B.E., outperforming Intel Duo Core (Woodcrest) for inputs of greater than 2K samples. We also optimize Discrete Wavelet Transform (DWT) in the context of JPEG2000 for the Cell/B.E. DWT has an abundant parallelism, however, due to the low temporal locality of the algorithm, memory bandwidth becomes a significant bottleneck in achieving high performance. We introduce a novel data decomposition scheme to achieve highly efficient DMA data transfer and vectorization with low programming complexity. Also, we merge the multiple steps in the algorithm to reduce the bandwidth requirement. This leads to a significant enhancement in the scalability of the implementation. Our optimized implementation of DWT demonstrates 34 and 56 times speedup using one Cell/B.E. chip to the baseline code for the lossless and lossy transforms, respectively. We also provide the performance comparison with the AMD Barcelona (Quad-core Opteron) processor, and the Cell/B.E. excels the AMD Barcelona processor. This highlights the advantage of the Cell/B.E. over general purpose multicore processors in processing regular and bandwidth intensive scientific applications.

Transverse vectorization of fast Fourier transforms on multicore architectures

Single‐instruction, multiple‐data (SIMD) multicore computing architectures, such as the IBM Cell Broadband Engine Architecture, offer new opportunities for quickly and efficiently calculating the 1D‐FFT of acoustic signals, as time‐sampled data arrays can be naturally partitioned across the multiple cores on which vectorized implementations of the FFT operate. Building on this parallel pipeline model, we consider the case that M data arrays of length N reside within each core. Whereas the cost of sequentially executing these M FFT's conventionally scales as αMNlog2N, we demonstrate a transverse vectorization solution whose cost scales as αβNlog2N, where α and β are constant scaling factors. Our approach makes use of the SIMD instruction set and large vector register file inherent to each core of the IBM Cell in order to calculate the FFT of M data arrays simultaneously. By efficiently using all the available vector registers in performing the FFT, this transverse SIMD vectorization solution further reduces the computational complexity of the conventional parallel pipeline model.

Accelerating Real-Time String Searching with Multicore Processors

String searching is at the core of tools used to search, filter, and protect data, but this has become increasingly difficult to do in real time as communication speed grows. The authors present an optimization strategy for a popular algorithm that fully exploits the IBM cell broadband engine architecture to perform exact string matching against large dictionaries and also offer various solutions to alleviate memory congestion.

High performance combinatorial algorithm design on the Cell Broadband Engine processor

The Sony–Toshiba–IBM Cell Broadband Engine (Cell/B.E.) is a heterogeneous multicore architecture that consists of a traditional microprocessor (PPE) with eight SIMD co-processing units (SPEs) integrated on-chip. While the Cell/B.E. processor is architected for multimedia applications with regular processing requirements, we are interested in its performance on problems with non-uniform memory access patterns. In this article, we present two case studies to illustrate the design and implementation of parallel combinatorial algorithms on Cell/B.E.: we discuss list ranking, a fundamental kernel for graph problems, and zlib, a data compression and decompression library. List ranking is a particularly challenging problem to parallelize on current cache-based and distributed memory architectures due to its low computational intensity and irregular memory access patterns. To tolerate memory latency on the Cell/B.E. processor, we decompose work into several independent tasks and coordinate computation using the novel idea of Software-Managed threads (SM-Threads). We apply this generic SPE work-partitioning technique to efficiently implement list ranking, and demonstrate substantial speedup in comparison to traditional cache-based microprocessors. For instance, on a 3.2 GHz IBM QS20 Cell/B.E. blade, for a random linked list of 1 million nodes, we achieve an overall speedup of 8.34 over a PPE-only implementation. Our second case study, zlib, is a data compression/decompression library that is extensively used in both scientific as well as general purpose computing. The core kernels in the zlib library are the LZ77 longest subsequence matching algorithm and Huffman data encoding. We design efficient parallel algorithms for these combinatorial kernels, and exploit concurrency at multiple levels on the Cell/B.E. processor. We also present a Cell/B.E. optimized implementation of gzip, a popular file-compression application based on the zlib library. For our Cell/B.E. implementation of gzip, we achieve an average speedup of 2.9 in compression over current workstations.

Exploring New Search Algorithms and Hardware for Phylogenetics: RAxML Meets the IBM Cell

Phylogenetic inference is considered to be one of the grand challenges in Bioinformatics due to the immense computational requirements. RAxML is currently among the fastest and most accurate programs for phylogenetic tree inference under the Maximum Likelihood (ML) criterion. First, we introduce new tree search heuristics that accelerate RAxML by a factor of 2.43 while returning equally good trees. The performance of the new search algorithm has been assessed on 18 real-world datasets comprising 148 up to 4,843 DNA sequences. We then present the implementation, optimization, and evaluation of RAxML on the IBM Cell Broadband Engine. We address the problems and provide solutions pertaining to the optimization of floating point code, control flow, communication, and scheduling of multi-level parallelism on the Cell.

CASL: A rapid-prototyping language for modern micro-architectures

We introduce CASL, the CoGenT Architecture Specification Language, a mixed behavioral–structure architecture description language designed to facilitate fast-prototyping and tool generation for computer architectures with deep pipelines and complicated timing. We motivate a number of CASL features using examples drawn from modeling the IBM Cell Broadband Engine, including implicit connection of components, pipeline support, dynamic information contexts, contention, and timing annotations. We also describe a number of different applications for CASL, including generating timing simulators and instruction schedulers.