Hybrid Space Vector Pulse Width Modulation Research Articles

Standby Losses Reduction Method for Flywheels Energy Storage System Based on Hybrid Space Vector Pulse Width Modulation

The flywheel energy storage system (FESS) can operate in three modes: charging, standby, and discharging. The standby mode requires the FESS drive motor to work at high speed under no load and has the longest operating time. Therefore, reducing the standby losses is of great significance for further promoting the application of FESS. In the paper, a novel modulation technique based on hybrid space vector pulse width modulation (HSVPWM) is proposed to reduce the standby losses of the FESS. By the reasonable arrangement of the zero vectors and non-zero vectors, the proposed method can reduce the switching frequency and eliminate the dead time, which reduces the standby losses of the FESS effectively. The modeling, simulation, and analysis verify the effectiveness of this method in reducing the standby loss of the FESS.

Zero-voltage and frequency pattern selection for DC-link loss minimization in PWM-VSI drives

The modulation of a voltage source inverter output causes losses and harmonic distortions on the load side and the DC-link capacitor due to the discrete switching of the semiconductors. High-frequent voltage pulses are digitally programmed to control the inverter output and determine the harmonic distortions. This paper presents an optimization in terms of pulse- and frequency-pattern selection for reducing load distortions while keeping DC-link losses minimal. In detail, the fact that pulse and frequency patterns are independent from each other is utilized and a modified three-zone hybrid space vector pulse-width modulation is proposed where optimal frequency patterns are selected for every carrier cycle. Simulations and experimental results validate the optimizations.

A Novel Low-Frequency Virtual Space Vector Modulation With the Improved Continuity of Output Average-Voltage and Bus Voltage Utilization for Single-Phase Neutral Point Clamped Three-Level Inverter

In the high-power superconducting fusion converter, the single-phase neutral point clamped (NPC) three-level converter is applied to replace the traditional thyristor converter using an integrated gate-commutated thyristor (IGCT) as a power device. The operating frequency of IGCT is usually lower, only a few hundred Hz. An optimized hybrid space vector pulsewidth modulation (SVPWM)-8H is proposed to solve the problems of discontinuous output average voltage, low dc bus voltage utilization rate, dead time compensation, and neutral point potential balance. The new sectors are inserted to make the range of output average voltage of adjacent sectors intersect, which improves the continuity of output average voltage. Furthermore, some sectors are composed of four vectors to reduce the minimum working time of redundant small vectors, improving the dc bus voltage utilization ratio and the converter’s performance. Moreover, by analyzing the influence of dead time on redundant small vectors, redundant vectors are rearranged to make redundant small vectors’ working time synchronously in sector and sector switching, which reduces the influence of dead time on neutral point potential balance. Finally, by analyzing the influence of dead time on the output average voltage, dead time compensation is applied, which reduces the difficulty of compensation implementation. Simulations and experiments verify the rationality of the optimized hybrid SVPWM-8H.

Hybrid SVPWM Modulation Strategy for Auxiliary Resonant Commutated Pole Inverter

Although the auxiliary resonant commutated pole inverter (ARCPI) can achieve soft-switching for main switches, the auxiliary commutation circuit (ACC) itself has a loss, especially under high frequency. To reduce the loss of ACC and optimize the efficiency of the ARCPI, this article proposes a hybrid space vector pulsewidth modulation (SVPWM) strategy. It can not only compensate for the influence of dead time but also reduce the operation times of the ACCs. First, the operation principles of an ARCPI are briefly analyzed. The topology can achieve soft-switching reliably for all switches with simplified ACCs. Then, appropriate zero vectors are designed for the hybrid SVPWM modulation strategy, which can guarantee that unnecessary switching actions are eliminated, and the switches in each bridge leg conduct symmetrically. Furthermore, the trigger pulse generation method for ACCs based on only one main switch is designed. Finally, the simulation and experimental results are given to demonstrate the validity of the proposed strategy.

Design space exploration of optimized hybrid SVPWM techniques based on spatial region for three level VSI

The performance of a multilevel inverter depends upon design and selection of an appropriate modulation technique. Space vector pulse width modulation (SVPWM) technique offers more flexibility than other pulse width modulation (PWM) techniques. However, conventional SVPWM technique becomes more complex for multilevel inverter because of increased number of space vectors and redundant switching states. This paper presents a design space exploration method of hybrid SVPWM techniques for three level voltage source inverter (VSI) to reduce total harmonic distortion (THD) and switching loss over wide linear modulation range. A new parameter Harmonic Loss (product of weighted total harmonic distortion factor of the line voltage (Vwthd) and normalized switching loss) is introduced as an objective function, and a spatial region identification algorithm is proposed to determine the optimized switching sequences for hybrid SVPWM technique. Two optimized hybrid SVPWM techniques are proposed based on the optimized switching sequences for three level VSI. The proposed hybrid SVPWM techniques are implemented on a low cost PIC microcontroller (PIC 18F452) and applied on an experimental prototype of three phase three level VSI with an induction motor as load. The experimental results are demonstrated to validate the performance of the proposed hybrid SVPWM techniques.

Maximum power point tracking-based hybrid pulse width modulation for harmonic reduction in wind energy conversion systems

Reduction of total harmonic distortion (THD) in fundamental output voltage and current in wind energy conversion systems (WECS) is the primary objective of this research paper. Reduction of distortion effects help in regulating the output voltage to a great extent. The paper suggests a novel perturb-and-observe (P&O)-based maximum power point tracking (MPPT) for the front-end single-ended primary-inductor converter (SEPIC), in an effort to exploit the maximum power from the available wind source. It further involves a hybrid space vector pulse width modulation (HSVPWM) scheme for generating the pulses to switches in the voltage source inverter (VSI), to improve the quality of the output AC power. It examines the performance through simulation in the MATLAB platform over a range of operating loads to illustrate the benefits of the scheme, in terms of a lower THD. The experimental results obtained from a prototype serve to validate the simulated response and claim its suitability for use in real world applications.

A novel hybrid space vector-based modulation technique for power quality improvement in a wind energy conversion system

The paper develops a novel hybrid space vector pulse width modulation (HSVPWM) for improving the quality of power transfer from a permanent magnet synchronous generator (PMSG) based wind energy conversion system (WECS) to a three phase induction motor load. It includes a Vienna rectifier (VR) based ac-dc converter in the front end and a voltage source inverter (VSI) for providing the variable frequency, variable voltage requirements of the induction motor load. The Vienna rectifier attempts to offer almost a unity power factor and early sinusoidal input as the input to the VSI as part of resurrecting the shape of the supply side waveform to the motor. The formulation involves a three-phase three-level HSVPWM along with a novel hysteresis current control technique for generating the firing pulses to the power switches in the VSI. The simulation results reveal a higher fundamental component a lower total harmonic distortion (THD) and harmonic spread factor (HSF) for the inverter output voltage over the similar other pulse width modulation (PWM) schemes and allow it claim a space for its use in real world utilities.

Unified SVPWM Algorithm and Optimization for Single-Phase Three-Level NPC Converters

The high-order harmonics caused by the modulation strategy can deteriorate power quality. The harmonic characteristics of the carrier-based pulsewidth modulation are relatively fixed and difficult to optimize, while space vector pulsewidth modulation (SVPWM) has more flexibility. The unified SVPWM design method for single-phase three-level neutral-point clamped (NPC) converters is fully presented in this article. Based on the proposed unified SVPWM method, two existing traditional vector sequences are designed first, and then several advanced multisegment SVPWM algorithms are proposed. According to the particularity of the three-level NPC topology, two hybrid SVPWM algorithms are proposed to optimize harmonic performance. Moreover, the high-order harmonic characteristics and the number of switching actions are analyzed in detail for all SVPWM algorithm modes. In addition, these SVPWM algorithms are associated and unified by introducing weight coefficients of the redundant vectors. Simulation and experimental results verify the feasibility and effectiveness of the proposed SVPWM algorithms, which show that the proposed methods can optimize high-order harmonic distribution and reduce the line current harmonics.

Zero-Sequence Voltage Elimination for Dual-Fed Common DC-Link Open-End Winding PMSM High-Speed Starter–Generator—Part I: Modulation

In this paper, a dual-fed (DF) common dc-link topology open-end winding permanent magnet synchronous motor for aircraft high-speed starter–generator application is considered. While on one hand the common dc bus configuration significantly simplifies and reduces the costs of the topology, on the other hand it allows the zero-sequence current (ZSC) to flow freely in the system. High-speed machines are characterized by low phase inductance, which implies low zero-sequence impedance. A small time constant of the zero-sequence circuit produces a high-frequency, high-intensity ZSC ripple with the risk of harming the switching devices. This paper presents a novel hybrid space vector pulsewidth modulation that allows to instantaneously eliminate the zero-sequence voltage (ZSV) produced by the two voltage source converters (VSCs) by square wave modulating one of the two VSCs. The non-sinusoidal machine back electromotive force (EMF) has been considered and the effect of the converters’ dead time on the ZSV has been analyzed. The square-wave-modulated VSC uses insulated-gate bipolar transistor (IGBT) devices, whereas the other uses Silicon Carbide (SiC) technology. The proposed topology is tested through both simulations and experiments.

Hybrid SVPWM Scheme to Minimize the Common-Mode Voltage Frequency and Amplitude in Voltage Source Inverter Drives

In this paper, a hybrid space vector pulsewidth modulation synthesis is proposed to lower the frequency and amplitude of the common-mode voltage (CMV). The conventional space vector pulsewidth modulation (SVPWM) techniques for inverters generate a high-frequency CMV. The CMV causes significant bearing current flowing through the path to the ground and leads to premature bearing failure, especially in high switching frequency drive systems. Furthermore, previously proposed CMV reduction studies focus on the reduction of CMV amplitude, leaving a high-frequency CMV. The proposed control algorithm divides each sector in the space vector hexagon into three segments based on the modulation index and the angle of the reference voltage vector. In each segment, the space vectors that produce minimal CMV are selected to synthesize the reference voltage vector. A fair comparison with the conventional CMV reduction methods is made by comparing the CMV characteristics, harmonic distortion factor, dc current ripple, and the switching losses for each method. Both simulation and experimental results have validated the effectiveness of the proposed approach.

An Optimized Hybrid SVPWM Strategy Based on Multiple Division of Active Vector Time (MDAVT)

This paper presents a new advanced bus-clamped space vector pulsewidth modulation (SVPWM) technique to reduce line current harmonic distortion as well as switching loss. The proposed sequence introduces multiple division of active vector time (MDAVT) in a subcycle. An analysis of optimal subdivision of active vector dwell time is presented. Existing bus-clamping pulsewidth modulation techniques use double-switching clamping sequences, which use only one zero state and apply an active vector twice in a subcycle. The proposed MDAVT-based SVPWM technique presents a hybrid SVPWM technique. The additional switching is added when the fundamental voltage crosses zero. The switching patterns for the other two phases are not changed. The harmonic performance and switching loss characteristics of the proposed hybrid SVPWM techniques over the existing SVPWM is verified with experimental results on a 415-V, 2.2-kW induction motor drive.

An Improved Hybrid Space Vector PWM Technique for IM Drives

In this paper, an improved hybrid space vector pulse width modulation (HSVPWM) technique is proposed for IM (induction motor) drives. The basic principle involved in the proposed random pulse width modulation (RPWM) cuddled SVPWM is amalgamating the pre-calculated switching timings for various sections of hexagonal space vector boundary and the random selection of carrier between two triangular signals, in order to disband acoustic switching noise spectrum with improved fundamental component. The arbitrary selection between triangular carriers, which is decided by digital signal states (Low or High) of the linear feedback shift register (LFSR) based pseudo random binary sequence (PRBS) generator. The SVPWM offers a control degree of freedom in terms of positioning of vectors inside every sampling interval and hence it has six possible variants of the voltage vectors arrangements in each sector. The developed HSVPWM is thoroughly analyzed in using the MATLAB? based simulation for all SVPWM variants. From the simulation and experimental results viz. harmonic spectrum, harmonic spread factor (HSF), total harmonic distortion (THD) etc., and the superiority of the proposed scheme such as better utilization of DC bus and the randomization of the harmonic power are evidenced. For the practical implementation, Xilinx XC3S500E FPGA device has been used.

Adjustable Proportional Hybrid SVPWM Strategy for Neutral-Point-Clamped Three-Level Inverters

Neutral-point (NP)-clamped three-level inverter, which is a widely used topology of multilevel converters, suffers from the NP voltage drift as its main technical drawback. The nearest-three-virtual-vector (NTV2) modulation method can control the NP voltage balance for any load over the full range of inverter output voltage. However, compared with the nearest-three-vector (NTV) modulation method, NTV2 increases the switching frequency. This paper combines NTV2 with NTV, and the two methods are used alternately in a fundamental cycle. The duty-cycle coefficients of the redundant small vectors are analyzed to explore the intervals where NTV can control the NP voltage balance in a fundamental cycle. The proportional parameter, which represents the combination of the two methods in hybrid space vector pulsewidth modulation, can be selected to achieve a high-performance NP balance control and low switching frequency. The steady- and transient-state behaviors of the proposed strategy are analyzed in this paper. The experimental results verify the validity of the proposed strategy.