Hybrid Single-electron Transistor Research Articles

CMOS compatible manufacturing of a hybrid SET-FET circuit

This study analyzes feasibility of complementary metal–oxide–semiconductor (CMOS)-compatible manufacturing of a hybrid single electron transistor–field effect transistor (SET-FET) circuit. The fundamental element towards an operating SET at room temperature is a vertical nanopillar (NP) with embedded Si nanodot generated by ion-beam irradiation. The integration process from NPs to contacted SETs is validated by structural characterization. Then, the monolithic fabrication of planar FETs integrated with vertical SETs is presented, and its compatibility with standard CMOS technology is demonstrated. The work includes process optimization, pillar integrity validation, electrical characterization and simulations taking into account parasitic effects. The FET fabrication process is adapted to meet the requirements of the pre-fabricated NPs. Overall, this work establishes the groundwork for the realization of a hybrid SET-FET circuit operating at room temperature.

An electron turnstile for frequency-to-power conversion.

Single-electron transport relates an operation frequency f to the emitted current I through the electron charge e as I = ef (refs. 1-5). Similarly, direct frequency-to-power conversion (FPC) links both quantities through a known energy. FPC is a natural candidate for a power standard resorting to the most basic definition of the watt: energy emitted per unit of time. The energy is traceable to Planck's constant and the time is in turn traceable to the unperturbed ground state hyperfine transition frequency of the caesium 133 atom. Hence, FPC comprises a simple and elegant way to realize the watt6. In this spirit, single-photon emission7,8 and detection9 at known rates have been proposed as radiometric standards and experimentally realized10-14. However, power standards are so far only traceable to electrical units, that is, to the volt and the ohm6,15-17. In this Letter, we demonstrate an alternative proposal based on solid-state direct FPC using a hybrid single-electron transistor (SET). The SET injects n (integer) quasi-particles (QPs) per cycle into the two superconducting leads with discrete energies close to their superconducting gap Δ, even at zero source-drain voltage. Furthermore, the application of a bias voltage can vary the distribution of the power among the two leads, allowing for an almost equal power injection nΔf into the two. While in single-electron transport current is related to a fixed universal constant (e), in our approach Δ is a material-dependent quantity. We estimate that under optimized conditions errors can be well below 1%.

Exploring the Influence of Variability on Single-Electron Transistors Into SET-Based Circuits

We analyze the performance of hybrid single-electron transistor (SET)–FET circuits when different variability sources are considered, e.g., SET’s quantum dot location and FET device dimension variations. For the FET device, FinFET and vertical nanowire configurations have been studied. The hybrid SET–FET circuits with both SET and FET in vertical topology depict the best circuit performance and the highest integration level. The variability impact on different SET-based circuits has been analyzed, including negative differential resistance and logic inverters.

Recovery of SINIS turnstile accuracy in a strongly nonequilibrium regime

We perform a theoretical study of nonequilibrium effects in charge transport through a hybrid single-electron transistor based on a small normal metal (N) island with the gate-controlled number of electrons, tunnel-coupled to voltage-biased superconducting (S) electrodes (SINIS). Focusing on the turnstile mode of the transistor operation with the gate voltage driven periodically, and electrons on the island being out of equilibrium, we find that the current quantization accuracy is a nonmonotonic function of the relaxation rate ${\mathrm{\ensuremath{\Gamma}}}_{\mathcal{F}}$ of the distribution function $\mathcal{F}(\ensuremath{\epsilon})$ on the island due to tunneling, as compared to the drive frequency $f$, electron-electron $1/{\ensuremath{\tau}}_{ee}$, and electron-phonon $1/{\ensuremath{\tau}}_{eph}$ relaxation rates. Surprisingly, in the strongly nonequilibrium regime, $f\ensuremath{\gg}{\mathrm{\ensuremath{\Gamma}}}_{\mathcal{F}}\ensuremath{\gg}{\ensuremath{\tau}}_{ee}^{\ensuremath{-}1},{\ensuremath{\tau}}_{eph}^{\ensuremath{-}1}$, the turnstile current plateau is recovered, similarly to the ideal equilibrium regime, ${\ensuremath{\tau}}_{eph}^{\ensuremath{-}1}\ensuremath{\gg}{\mathrm{\ensuremath{\Gamma}}}_{\mathcal{F}}$. The plateau is destroyed in the quasiequilibrium regime when the electron-electron relaxation is faster than tunneling.

Effect of photon-assisted Andreev reflection in the accuracy of a SINIS turnstile

We consider a hybrid single-electron transistor constituted by a gate-controlled normal-metal island (N) connected to two voltage-biased superconducting leads (S) by means of two tunnel junctions (SINIS), operated as a turnstile. We show that the exchange of photons between this system and the high-temperature electromagnetic environment where it is embedded enhances Andreev reflection, thereby limiting the single-electron tunneling accuracy.

Hybrid architecture for shallow accumulation mode AlGaAs/GaAs heterostructures with epitaxial gates

Accumulation mode devices with epitaxially grown gates have excellent electrical stability due to the absence of dopant impurities and surface states. We overcome typical fabrication issues associated with epitaxially gated structures (e.g., gate leakage and high contact resistance) by using separate gates to control the electron densities in the Ohmic and Hall bar regions. This hybrid gate architecture opens up a way to make ultrastable nanoscale devices where the separation between the surface gates and the 2D electron gas is small. In this work, we demonstrate that the hybrid devices made from the same wafer have reproducible electrical characteristics, with identical mobility and density traces over a large range of 2D densities. In addition, thermal cycling does not influence the measured electrical characteristics. As a demonstration of concept, we have fabricated a hybrid single-electron transistor on a shallow (50 nm) AlGaAs/GaAs heterostructure that shows clear Coulomb blockade oscillations in the low temperature conductance.

Characterization of aluminum oxide tunnel barriers by combining transport measurements and transmission electron microscopy imaging

We present two approaches for studying the uniformity of a tunnel barrier. The first approach is based on measuring single-electron and two-electron tunneling in a hybrid single-electron transistor. Our measurements indicate that the effective area of a conduction channel is about one order of magnitude larger than predicted by theoretical calculations. With the second method, transmission electron microscopy, we demonstrate that variations in the barrier thickness are a plausible explanation for the larger effective area and an enhancement of higher order tunneling processes.

Erratum: Corrigendum: Hybrid single-electron transistor as a source of quantized electric current

Nature Physics 4, 120–124 (2008); published online 9 December 2007; corrected after print 8 April 2014. In the version of this Letter originally published, discussions of SNS and NSN transistors were reversed in the captions of Figs 1–3, with concomitant errors in the main text where those figures were referred to.

Tunneling and relaxation of single quasiparticles in a normal-superconductor-normal single-electron transistor

We investigate the properties of a hybrid single-electron transistor, involving a small superconducting island sandwiched between normal metal leads, which is driven by dc plus ac voltages. In order to describe its properties we derive from the microscopic theory a set of coupled equations. They consist of a master equation for the probability to find excess charges on the island, with rates depending on the distribution of nonequilibrium quasiparticles. Their dynamics follows from a kinetic equation which accounts for the excitation by single-electron tunneling as well as the relaxation and eventual recombination due to the interaction with phonons. Our low-temperature results compare well with recent experimental findings obtained for ac-driven hybrid single-electron turnstiles.

Tunneling Rates of Electron Pumping in the R-SINIS Transistor

We consider the influence of the electromagnetic fluctuations on the transport properties of a hybrid single electron transistor, consisting of superconducting electrodes and a normal-metal island, when operated as a turnstile. We derive the analytic expressions for the rates near the thresholds of single electron tunneling, Andreev reflection, and Cooper-pair–electron cotunneling processes. These results show that the dissipative on-chip impedance suppresses the rates of the undesirable higher-order tunneling processes much stronger than the single electron tunneling which can therefore be utilized to increase the accuracy of such a device in quantum metrological applications.

Cotunneling suppression in a hybrid single-electron transistor by a dissipative electromagnetic environment

We study electron transport through a hybrid single-electron transistor, consisting of a superconducting island and normal-metal electrodes, in the Coulomb blockade regime. We derive analytic expressions for the elastic and inelastic cotunneling currents, which exhibit power law suppression induced by the dissipative electromagnetic environment. The results can be used to improve the accuracy of hybrid devices employed in electrical metrology and for noise measurements in quantum information processing.

A study on hyperchaotic system implemented by SETMOS

In this paper, we proposed a hardware implementation method for generating a sandwich hyperchaotic attractor. Based on the negative differential conductance (NDR) characteristic of hybrid single-electron transistor and complimentary metal–oxide–semiconductor (SETMOS) architecture, Saito hysteresis chaos generator (SHCG) was constructed using a cellular neural network (CNN). Complex dynamical behaviors of the hyperchaotic system were investigated by means of bifurcation diagram, Lyapunov exponent spectrum, Poincaré mapping and power spectrum. Numerical simulations verify the theoretical analysis and design method and show that the implemented hyperchaotic circuit works very well.

Implementation of multi-scroll Chua’s circuit by hybrid single electron transistor and metal oxide semiconductor structure

Based on the structure of cellular neural network, multi-scroll Chua’s circuit is implemented by the nanoelectronic device of hybrid single electron transistor and metal oxide semiconductor (SETMOS) structure with its negative differential resistance characteristic. The basic dynamical properties, including phase portrait, bifurcation diagram, Lyapunov exponent spectrum, Poincaré mapping and power spectrum are studied by theoretic analysis and numerical simulation. The validity and the feasibility of three-order Chua’s circuit with four scrolls are further confirmed by the circuit simulation experiment. Finally, the results show that the negative differential resistance characteristic of SETMOS determines complex dynamical behaviors of multi-scroll Chua’s circuit. Also, the designed circuit has simple structure and is easy to realize.

Characteristic of hybrid single electron transistor and metal oxide semiconductor structure in Chua’s circuit

The negative differential resistance (NDR) characteristic equation of single electron transistor and metal oxide semiconductor (SETMOS) hybrid structure is simplified by a fitting method. And a new approach to designing multi-scroll chaotic circuit with SETMOS is proposed. The effect of NDR characteristic on the equilibrium point of multi-scroll Chua’s circuit is analyzed both qualitatively and quantitatively. The results show that the unidirectional motions of radial contract and axial tension occur in the negative sections of multi-scroll Chua’s circuit, whereas in the positive sections appear the scroll motions of radial tension and axial contract. The result provides theoretical basis for the construction of multi-scroll chaotic circuits and the further study of their complex dynamical behaviors.

Single-Electronic Radio-Frequency Refrigerator

We demonstrate experimentally that a hybrid single-electron transistor with superconducting leads and a normal-metal island can be refrigerated by an alternating voltage applied to the gate electrode. The simultaneous measurement of the dc current induced by the rf gate through the device at a small bias voltage serves as an in situ thermometer.

Pumping properties of the hybrid single-electron transistor in dissipative environment

Pumping characteristics were studied of a hybrid normal-metal/superconductor single-electron transistor embedded in high-Ohmic environment. Two 3 μm long microstrip resistors of CrOx with a sum resistance R≈80 kΩ were placed adjacent to the transistor. Substantial improvement of pumping and a reduction of the subgap leakage were observed in the low-megahertz range. At higher frequencies (0.1–1 GHz), pumping performance deteriorated compared to reference devices without resistors by the slowdown of tunneling and by electronic heating.

Quantized current of a hybrid single-electron transistor with superconducting leads and a normal-metal island

We discuss the operation of the superconductor–insulator–normal-metal–insulator–superconductor (SINIS) turnstile. This voltage-biased hybrid single-electron transistor (SET) provides current quantization even with only one radio-frequency (rf) control parameter, namely the gate voltage of the single island. We give an overview of the main error mechanisms of the turnstile and consider its feasibility as a quantum current standard. We also present experimental results of pumping with the SINIS structure which show decreased leakage current compared to earlier measurements with the opposite NISIN structure.

Implementation and application of cellular neural networks based on single electron device

This paper realizes cellular neural networks using the characteristic of negative differential resistance of hybrid single electron transistor and complementary metallic oxide semiconductor field effect transistor structure. The main building blocks consisting of cell core circuit, A and B template circuits are designed. Then a cellular neural network (CNN) is built and its application in image processing is studied. The computer simulation shows that the designed circuits are suitable for CNN implementation owing to its simple structure, low power dissipation and fast response. It could be used to form CNN of various scales so as to further increase the density of integrated circuits.

Hybrid single-electron transistor as a source of quantized electric current

The basis of synchronous manipulation of individual electrons in solid-state devices was laid by the rise of single-electronics about two decades ago. Ultra-small structures in a low temperature environment form an ideal domain of addressing electrons one by one. A long-standing challenge in this field has been the realization of a source of electric current that is accurately related to the operation frequency $f$. There is an urgent call for a quantum standard of electric current and for the so-called metrological triangle, where voltage from Josephson effect and resistance from quantum Hall effect are tested against current via Ohm's law for a consistency check of the fundamental constants of Nature, $\hbar$ and $e$. Several attempts to create a metrological current source that would comply with the demanding criteria of extreme accuracy, high yield, and implementation with not too many control parameters have been reported. However, no satisfactory solution exists as yet despite many ingenious achievements that have been witnessed over the years. Here we propose and prove the unexpected concept of a hybrid metal-superconductor turnstile in the form of a one-island single-electron transistor with one gate, which demonstrates robust current plateaus at multiple levels of $ef$ within the uncertainty of our current measurement. Our theoretical estimates show that the errors of the present system can be efficiently suppressed by further optimizations of design and proper choice of the device parameters and therefore we expect it to eventually meet the stringent specifications of quantum metrology.