Hybrid Digital Pulse Width Modulator Research Articles

Digital V2 Controller IC Using Delta Operator and Improved Average Predictive Control for DC–DC Converters With Fast Transient Response

Owing to its fast transient response, the V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> control technique for switching converters has wide potential application prospects. In this article, we present a digital V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> controller integrated circuit (IC) for dc–dc switching converters to improve the transient response. The controller IC consists of two compensators and some ancillary circuits, specifically a proportion-integral-differential (PID) compensator and a predictive control compensator, as well as an analog-to-digital converter (ADC) and a digital pulsewidth modulator (DPWM). The PID compensator is designed based on the delta operator instead of the conventional shift operator, which can improve the stability of the converter and reduce hardware costs. The predictive control compensator uses an improved average predictive control strategy to enhance the transient response. A 6-b delay-line window ADC with a differential bias circuit is proposed to improve the ADC linearity. An 11-b hybrid DPWM, which consists of a counter and a segmented delay line with a delay-locked loop (DLL), is proposed to relieve the conflict between the die area and DPWM linearity. A prototype of the digital V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> controller IC was fabricated using the 180-nm CMOS process, which was applied to a buck dc–dc switching converter to verify its performance. The experimental results show that an excellent transient response was achieved.

Design and implementation of a hybrid DPWM under 50 ps resolution based on general‐purpose FPGA

SummaryHigh‐resolution pulse width modulators are used widely in different fields of electrical engineering, such as dimming of light‐emitting diode (LED) lighting, motor control, RF modulators, audio amplifiers, and switch‐mode power supplies. To realize a high‐resolution digital pulse‐width modulator (DPWM) in a limited inner system clock, a simple implementation of a hybrid DPWM with the resolution under 50 ps based on a general‐purpose field‐programmable gate array (FPGA) is described. The multiplexer device implementing the fast carry‐chain path and an AND gate controlling the selection input are used as a delay unit. The manual routing or placement is not required in the proposed approach, which just needs some conditional constraints. Some different conditional constraints influencing the monotonicity and resolution of DPWM are discussed. Finally, a 1 MHz switching frequency DPWM with 40 ps resolution is experimentally demonstrated, with high monotonicity and linearity. Further, a synchronous buck with and without this high‐resolution DPWM is experimentally compared to illustrate the regulation resolution.

A high‐resolution hybrid digital pulse width modulator with dual‐edge‐triggered flip‐flops and hardware compensation

SummaryIn this paper, a hybrid architecture of digital pulse width modulator (DPWM) which applies a counter, a phase‐shifted circuit, and a carry chain is proposed. Dual‐edge‐triggered flip‐flops are used in the phase‐shifted circuit to generate signals with 45° phase shift, which not only improves the resolution of the DPWM but also reduces the resource consumption in the carry chain. Furthermore, a hardware compensation method is used to solve the duty cycle increment phenomenon that affects the regulation accuracy of converter. An 11‐bit DPWM with the proposed architecture is implemented and tested by Xilinx Artix‐7 FPGA. The experimental results show a high resolution of 32 ps and a good linearity where R2 is 0.99 and verify the effect of duty cycle compensation.

Hybrid Linearized Class-BD Double Sided (LBDD) Digital Pulse Width Modulator (DPWM) for Class-BD Audio Amplifiers

The paper presents an original architecture and implementation of 9-bit LBDD hybrid DPWM circuit for Class-BD digital audio amplifier. The input PCM signals are directly transformed into 24-bit LBDD DPWM signals and then are requanized to the 9-bit digital outputs using noise-shaping process to support high fidelity with practical values of time resolution, and finally are converted by the DTCs into the two physical trains of 1-bit PWM signals. The architecture of the proposed Class-BD hybrid DPWM circuit is composed of two Class-AD ones. The hybrid quantizer converts 6 MSB bits using counter method, based on the STM32F407xx microcontroller, while the remaining 3 LSB bits - using a method based on the Programmable Tapped Delay Line (PTDL). All necessary time waveforms are generated on the base of the internal microcontroller oscillator 168 MHz. The proposed 9-bit Class-DB DPWM circuit allows to attain SNR of 110 dB and THD about 0,2% within the audio baseband, at switching frequency of 328.1 kHz, clock frequency of 42 MHz and modulation index M = 0.95. Basic verification of algorithm and circuit operation as well as simulation and preliminary experimental results have been performed.

FPGA Based Digital Controller for DC-DCBuck Converter

This paper presents performance analysis of Digital PWM control mode in DC-DC buck converter in terms of power efficiency, line regulation and load regulation. Matlab/Simulink Models are built to facilitate the analysis of various effects on power loss and conversion efficiency, including different load conditions. It introduces a fully synthesizable hybrid digital pulse width modulator (DPWM) utilizing Σ‒Δ modulation technique to achieve best possible resolution of 12 bit. A type-II compensator is designed for the buck converter in order to achieve a stable closed loop operation with desired performance. FPGA implementation is carried out for both type-II compensator and DPWM using Xilinx system generator tool. A load regulation of 4% with a response time of 200us is achieved for a load change of 0.4A to 0.8A.A line regulation of 2% with a response time of 100us is achieved for a line voltage change of 3 to 4.5V. A Graph of conversion efficiency versus load current is obtained.

Design of low-power hybrid digital pulse width modulator with piecewise calibration scheme

A low-power hybrid digital pulse width modulator (DPWM) is proposed in the paper. Owing to the piecewise calibration scheme, the delay time of delay line is locked to target frequency. The delay line consists of two piecewise lines with different control codes. The delay time of each cell in one sub-delay-line is longer than the last significant bit (LSB) of DPWM, while the delay time of each cell in the other sub-delay-line is shorter than LSB. Optimum linearity is realised with minimum standard cells. Simulation results show that the differential nonlinearity and integral nonlinearity are improved from 5.1 to 0.4 and from 5 to 1.3, respectively. The DPWM is fully synthesised and fabricated in a 90-nm CMOS process. The proposed DPWM occupies a silicon area of 0.01 mm2, with 31.5 μw core power consumption. Experimental results are shown to demonstrate the 2-MHz, 10-bit resolution implementation. Pulse width histogram is firstly introduced to characterise the linearity of the DPWM.

A 12-bit Hybrid Digital Pulse Width Modulator

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

Hybrid DPWM implementation using coarse and fine programmable ADLL

In the paper we propose a novel architecture and implementation of 11-bit Digital Pulse Width Modulator (DPWM) circuit based on previously known building blocks. Linearized Class-AD Double-sided (LADD) algorithm has been used to calculate the DPWM signals of the 11-bit resolution hybrid DPWM for a Class-AD digital audio amplifier. Noise-shaping process is used to support high fidelity with practical values of time resolution. The proposed DPWM circuit is composed of 8-bit counter and Analog Delay Locked Loop (ADLL) using 4-bit tapped delay line. A dual ADLL employing coarse and fine programmable delay element is used to adjust the delay time of delay line and lock it to required time. The coarse- as well as fine-delay lines are implemented as a cascade of variable-delay elements based on shunt capacitor delay element or single-ended Schmitt trigger. The proposed 11-bit DPWM circuit, at a switching frequency of 352.8kHz and clock generator frequency of 90.3MHz allows us to attain SNR of 120dB and THD of the output signal less than 0.1% within the audio baseband and modulation index M=0.95. Basic verification of circuit manufacturability and simulation results (Monte Carlo analysis) for real CMOS process are presented.

Design and implementation of a digitally controlled single‐inductor dual‐output (SIDO) buck converter

SUMMARYThis paper describes design and implementation of a digitally controlled single‐inductor dual‐output (SIDO) buck converter operating in discontinuous conduction mode. This converter adopts time‐multiplexing control in providing two independent output voltages using only an inductor. The design issues of the digital controller are discussed, including static and dynamic characteristics. Implementation of the controller, a modified hybrid digital pulse width modulator and a single look‐up table are developed. The digital controller was implemented on a field‐programmable gate array‐based control board. Experimental results demonstrating system validity are presented for a SIDO buck converter with nominal 3.6 V input voltage, and the outputs are regulated at 1.8 and 2.2 V. Copyright © 2012 John Wiley &amp; Sons, Ltd.

Digital Controller for DVS-Enabled DC–DC Converter

A high-frequency digital controller that includes an optimized analog-digital converter (ADC) with a novel formulation of digital error value based on target clock frequency and converter output voltage is presented in this paper. A programmable look-up table-based digital compensator is implemented for fast processing the feedback error. Limitations of a hybrid digital pulsewidth modulator (DPWM) at high frequency are addressed and solved by an edge-triggered logic. Support for process, voltage, and temperature variations is incorporated in the integrated design. Target clock frequency denotes the frequency of the signal which is driven by dynamic voltage scaling (DVS) processor and corresponds to the reference value of the regulated output voltage. This work realizes the classical digital controller design implementation of a target frequency to minimum required regulated voltage for DVS-enabled adaptive DC-DC converter. A synchronous buck converter of 1 MHz switching frequency and the proposed delay-line-based optimized ADC have been fabricated for realizing and verifying the complete digital controller on a field-programmable gate array-based closed-loop prototype. Experimental results are presented, which demonstrate the fast dynamic response achieved for target clock frequency in the range of 6-16 MHz, corresponding to the regulated output voltage range of 1.6-3.2 V. The complete design of digital controller has been implemented in 0.5 ¿m CMOS technology using Cadence and Synopsys tools. The active on-chip area of the proposed delay-line ADC, digital compensator, and edge-triggered hybrid DPWM are 0.08, 0.28, and 0.07 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> respectively.

Analysis of Process-Dependent Maximal Switching Frequency, Choke Effect, and Its Relaxed Solution in High-Resolution DPWM

This letter uses the fanout-of-4 (FO4) metric to analyze the semiconductor process (SP) dependent maximal switching frequency (MSF) of a digital pulsewidth modulator (DPWM). After discussing the choke effect in a self-oscillating hybrid (SOH) DPWM and its impact on MSF, this letter further shows that separating the voltage-controlled oscillator (VCO) and the delay mux line is an effective way to relax the choke effect so that the MSF in the SOH could be almost doubled, together with 10%-20% power saving. Taking a low-cost AMI06 SP and 9-bit-resolution specification as an example, this letter predicts that 8 MHz switching frequency could be achieved with the proposed SOH. The SOH chip was custom-designed and fabricated in a 0.703 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die via the metal oxide semiconductor implementation service (MOSIS) educational program. The chip test demonstrated that the MSF is 7.4 MHz with 1.07 mA power consumption, and the adjustable switching frequency range is from 1.8 to 7.4 MHz.