Hot-electron Reliability Research Articles

Investigation of dynamic ron stability and hot electrons reliability in normally-off AlGaN/GaN power HEMTs

The current collapse and hot electron effect of 100 V normally-off GaN power HEMTs are investigated. The 100 V GaN-on-Si power HEMTs are fabricated on an industrial 200 mm Si CMOS compatible technology platform. The double pulse test (DPT) and the dynamic high temperature operating life (DHTOL) test are implemented to verify the dynamic on-resistance (dynamic Ron) stability. Wafer level hot electron reliability test is performed to investigate the effect of high electric field and high current on GaN power HEMT. It is proved that the dynamic Ron stability of 100 V GaN power HEMT is qualified (Ron/Rini, static < 1.2) when the drain-source off-state voltage (Vdsoff) is less than 80 V. It is shown that the dynamic Ron degradation of GaN device is recoverable by means of annealing. Hot electrons reliability is dominated by the high electric field at drain edge and the high current which is source injected electrons flowing to the drain. It is demonstrated that the Vth drift and Ron degradation are extraordinary serious under semi on-state stress condition with Vdsoff = 60 V.

Efficacy of back barrier engineered Π-gate InAlN/GaN high electron mobility transistors for high-power applications

This work investigates thin-barrier InAlN/GaN high electron mobility transistors (HEMTs) for high-power applications through technology computer-aided design (TCAD) simulations. To begin with, the TCAD simulations were first calibrated with an in-house fabricated InAlN HEMT sample for both DC and pulsed characteristics. The thin-barrier InAlN/GaN HEMTs showed a large leakage current through the gate electrode due to high gate injection, which severely degrades the breakdown characteristics of the device and thus acts as a bottleneck for high-power applications. To improve the two-dimensional electron gas confinement, and consequently reduce the bulk leakage, a back-barrier technique was used. The resistive GaN buffer was replaced with an AlGaN back-barrier that improved the breakdown characteristics at the cost of output power density. Thus, to scale up the output power density and further optimize the breakdown characteristics a Π-shaped gate was introduced to limit the gate leakage current through the InAlN barrier by virtue of its improved hot electron reliability. Coupled with the AlGaN back-barrier, the Π-gate significantly improved the breakdown characteristics to achieve high output power densities, albeit with minor trade-offs to the device gain. To elucidate the compatibility with high-power applications, all the device architectures were dynamically characterized by pulsed I–V simulations and the trap-related dispersive effects were investigated. The Π-shaped gate coupled with an AlGaN back-barrier outperforms conventional architectures by exercising superior electrostatic control over the channel and exhibiting a high linearity for high-power millimeter-wave applications.

Electrothermal analysis of novel N-P-P FinFET with electrically doped drain: a dual material gate device for reliable nanoscale applications

In this paper, we offer a new structure of N+-P-P Fin Field Effect Transistor (FinFET) with a dual material gate in which the drain side P–N junction has been physically removed. The P-type drain consists of two parts, depletion region (DR) and electrically doped (ED) area, where the ED region is surrounded by an extra gate with optimized length and appropriate work function made of barium (B-gate). The ED region located under the B-gate is converted to N+ drain using the charged plasma (CP) concept to design the CP-FinFET. Improved ability to control the hot carrier effect by amending the critical electric field is the main idea of this work. The p-type depletion region (DR) created between the silicon active layer and electrically doped drain eliminates the gate-drain overlap and reduces the charge sharing and short channel effects (SCE). The modified electric field in the DR region offers advantages including improved hot-electron reliability and high-performance devices. Therefore, in the CP-FinFET the degradation mechanism improves due to the hot carrier effect (HCE) reduction. Indeed, the improvement in device performance is investigated using three-dimensional Atlas simulator with concentrating on the gate current, off-state current, reliability, electron temperature and gate induced drain leakage (GIDL). The comparison results demonstrate the superiority of the proposed structure as a high-efficiency device to design reliable Complementary metal–oxide–semiconductor circuits in nanoscale.

A novel double gate MOSFET by symmetrical insulator packets with improved short channel effects

ABSTRACTIn this article, we study a novel double-gate SOI MOSFET structure incorporating insulator packets (IPs) at the junction between channel and source/drain (S/D) ends. The proposed MOSFET has great strength in inhibiting short channel effects and OFF-state current that are the main problems compared with conventional one due to the significant suppressed penetrations of both the lateral electric field and the carrier diffusion from the S/D into the channel. Improvement of the hot electron reliability, the ON to OFF drain current ratio, drain-induced barrier lowering, gate-induced drain leakage and threshold voltage over conventional double-gate SOI MOSFETs, i.e. without IPs, is displayed with the simulation results. This study is believed to improve the CMOS device reliability and is suitable for the low-power very-large-scale integration circuits.

A novel fin field effect transistor by extra insulator layer for high performance nanoscale applications

The present study reveals the novel structure of nanoscale silicon-on-insulator fin field effect transistor (FinFET) in which an extra insulator layer (EIL) is injected into the silicon active layer. The key idea in this work is to control the hot electron effect by reducing the critical electric field near the drain region. The high-k dielectric $$\hbox {HfO}_{2}$$HfO2 is located between the silicon active layer and drain region under the gate oxides, where the average lateral electric field in the post-saturation region is high due to the function of the gate. The results of simulations reveal improvement in the hot electron reliability of EIL---FinFET in comparison to conventional FinFET (C-FinFET). In the proposed structure, the insulator region $$\hbox {HfO}_{2}$$HfO2 decreases the electric field in the channel and drain regions, especially near the Fin corners. Therefore, reducing the hot carrier effect (HCE), brings about more efficiency in the operation of the proposed structure in comparison with that of C-FinFET. Furthermore, the performance improvement of the proposed structure has been investigated using three-dimensional and two-carrier device simulator. In addition to that, the HCE, off current, and gate current in both the devices are compared to demonstrate the high reliability of the EIL---FinFET in complementary metal oxide semiconductor devices.

Hot-electron reliability improvement using perhydropolysilazane spin-on-dielectric passivation buffer layers for AlGaN/GaN HEMTs

We investigate the effects of perhydropolysilazane spin-on-dielectric (SOD) buffer layer adopted prior to Si3N4 passivation on the dc drain current level and degradation after the electrical stress in the AlGaN-GaN high electron mobility transistors (HEMTs). The SOD-buffered HEMTs show ∼1.6 times greater drain current densities (∼257 mA/mm) than those of the devices with conventional-Si3N4 passivations (∼155 mA/mm). After the hot electron stresses (step-wise and constant) applied to the devices, it is also found that the SOD-buffered structure produces greatly improved device reliability in terms of the dc current collapse (15% for step-stress and constant stress) compared to the conventional structure (25% for each case). We propose that the enhancement of SOD-buffered structure in dc current collapse is due to the reduction in surface state density at the passivation interface and the suppressed electron trapping.

SOI MOSFET with an insulator region (IR-SOI): A novel device for reliable nanoscale CMOS circuits

Abstract Device performance in the electronic circuits degrades with elapsed time. Therefore it is important to design a new device to have a reliable performance. In this paper, we present the unique features exhibited by a novel nanoscale silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) in which the silicon active layer consists of an insulator region (IR-SOI). The high- K dielectric HfO 2 as an insulator material is located in the silicon active layer and drain region. Our simulation results demonstrate that this leads to improve the hot electron reliability of the IR-SOI in comparison with the conventional SOI-MOSFET (C-SOI). The insulator region HfO 2 considerably decreases the electric field in the channel and drain regions. Therefore, the degradation mechanism in the proposed structure is lower than that in the C-SOI structure because of reduction of hot carrier effect (HCE). Also using two-dimensional and two-carrier device simulation, we have investigated the improvement in device performance focusing on the HCE, off current, gate current and gate induced drain leakage (GIDL) which can effect on the reliability of the CMOS devices.

Experimental evaluation of hot electron reliability on differential Clapp-VCO

This paper studies the hot-carrier stressed property of a series-tuned all-n core voltage controlled oscillator (VCO). A differential Clapp-VCO has been successfully implemented in the 0.13m CMOS process and it uses a series-tuned resonator. Two single ended nMOS-core Clapp-VCOs are used to form a differential VCO by the aid of a cross-coupled nMOS pair and a transformer. The measured results show that the fresh Clapp-VCO operates from 18.8 to 22.2GHz and hot-carrier stressed experimental data indicate that the damage increases the oscillation frequency and degrades the phase noise of oscillator. Mixed-mode simulation results are used to show the hot-carrier physics to the circuit.

Impact of strain on hot electron reliability of dual-band power amplifier and integrated LNA-mixer RF performances

Abstract Channel hot-electron-induced degradation on strained MOSFETs is examined experimentally. BSIM stressed model parameters are extracted from measurement and used in Cadence SpectreRF simulation to study the impact of channel hot electron stress on dual-band class-E power amplifier and integrated low-noise amplifier-mixer RF performances. Channel hot electron effect decreases power efficiency of dual-band class-E power amplifier and increases the noise figure of low-noise amplifier-mixer combined circuit.

A Novel Nanoscale 4H-SiC-on-Insulator MOSFET Using Step Doping Channel

In this paper, we present the unique features exhibited by a novel step doping channel technique in nanoscale silicon carbide metal-oxide-semiconductor field-effect transistors (SDC-MOSFETs) for reaching a suitable threshold voltage upon device scaling and reliability improvement. The device demonstrates large enhancements in performance areas such as output resistance, hot-electron reliability, and threshold voltage upon channel-length or drain-voltage variation. Also, we describe an optimization technique in SDC-MOSFET for improving the threshold-voltage characterization. It was also found that the device performance is very much dependent upon the SDC region parameters. Results show that the most difficult problem of using silicon carbide in VLSI circuits could be solved and that the proposed silicon carbide MOSFETs can work very well in the nanoscale regime.

Hot-Electron-Induced Degradation in BCB- and SiN-Passivated $\hbox{Al}_{0.25}\hbox{Ga}_{0.75}\hbox{As/In}_{0.2}\hbox{Ga}_{0.8}\hbox{As}$ PHEMTs

In this paper, the hot-electron-induced degradation in Al0.25Ga0.75As/In0.2Ga0.8As pseudomorphic high-electron-mobility transistors passivated by low-k benzocyclobutene (BCB) has been investigated. Compared to the more commonly used silicon nitride (SiN), BCB has a lower dielectric constant and loss tangent and is becoming popular for passivation. However, its influence on the device hot-electron reliability has not been extensively studied so far. This paper examines the changes in the device dc drain-current, transconductance, and OFF-state breakdown voltages before and after hot-electron stress. For comparison purposes, the results for a device passivated using SiN have been included. The dominant mechanism that is responsible for the degradation in each technology has also been proposed and explained.

Considerations for evaluating hot-electron reliability of strained Si n-channel MOSFETs

Tensile-strained Si on relaxed Si 1− x Ge x buffers has emerged as an important channel material for improving CMOS performance. The ability of tensile-strained Si to dramatically improve MOSFET drive currents has received much attention in the literature in recent years, but little is known about its reliability characteristics. In this review we discuss some of the issues that should be considered in the analysis of hot-electron reliability of strained Si n-channel MOSFETs.

Improved Hot-Electron Reliability in Strained-Si nMOS

Strained-Si/relaxed-Si/sub 1-x/Ge/sub x/ structures provide a viable means of improving CMOS performance. For nMOS devices, the tensile strain in pseudomorphic Si on relaxed-Si/sub 1-x/Ge/sub x/ splits the six-fold degeneracy of the conduction band minimum, rendering increased electron mobility due to a lower in-plane effective mass and reduced intervalley scattering. In this paper, in addition to confirming enhanced performance for biaxial-strained-Si nMOS, we present hot-electron degradation characteristics for the first time, showing improvement over bulk Si.

The effects of channel boron-doping on the performance and hot electron reliability of N-channel trench UMOSFETs

We report on the effects of channel doping on the performance and hot electron stress (HES) reliability of U-shaped trench gate metal-oxide–silicon field-effect transistors (UMOSFETs). The boron-doped n-channel UMOSFETs are examined using transistor parameters and charge pumping current measurements. It is shown that increasing boron doping of the channel degrades UMOSFETs performance via decreasing the effective electron mobility in the channel and increasing the electron drift resistance in the drain region of the device. It is shown that increasing the boron doping of the channel does not increase interface trap density, which is a major cause for mobility reduction in MOSFETs: instead, ionized impurity scattering in the channel as well as the electric field transverse to the device channel, both of enhanced by doping, are argued to primarily cause the observed degradation in the electron mobility. The UMOSFETs response to HES is observed to be dependent on the doping level of the channel and is discussed in terms of the hot electron energy and its influence by channel doping.

Optimization of FIBMOS Through 2D Silvaco ATLAS and 2D Monte Carlo Particle-based Device Simulations

Focused Ion Beam MOSFETs (FIBMOS) demonstrate large enhancements in core device performance areas such as output resistance, hot electron reliability and voltage stability upon channel length or drain voltage variation. In this work, we describe an optimization technique for FIBMOS threshold voltage characterization using the 2D Silvaco ATLAS simulator. Both ATLAS and 2D Monte Carlo particle-based simulations were used to show that FIBMOS devices exhibit enhanced current drive capabilities when compared to normal MOSFETs. It was also found that the device performance is very much dependent upon the FIB implant profile. High and narrow doping of the FIB implant leads to high drain current and low hot carrier reliability, whereas low and wide doping gives rise to lower drain current and higher hot carrier reliability.

Reliability of ultrathin silicon dioxide under combined substrate hot-electron and constant voltage tunneling stress

An experimental investigation of breakdown and defect generation under combined substrate hot-electron and tunneling electrical stress of silicon oxide ranging in thickness from 2.0 nm to 3.5 nm is reported. Using independent control of the gate current for a given substrate and gate bias, the time-to-breakdown of ultrathin silicon dioxide under substrate hot-electron stress is observed to be inversely proportional to the gate current density. The thickness dependence (2.0 nm to 3.5 nm) of substrate hot-electron reliability is reported and shown to be similar to constant voltage tunneling stress. The build-up of defects measured using stress-induced-leakage-current and charge-pumping for both tunneling and substrate hot-electron stress is reported. Based on these and previous results, a model is proposed to explain the time-to-breakdown behavior of ultrathin oxide under simultaneous tunneling and substrate hot-electron stress. The results and model provide a coherent understanding for describing the reliability of ultrathin SiO/sub 2/ under combined substrate hot-electron injection and constant voltage tunneling stress.

Improved hot-electron reliability in high-performance, multilevel-metal CMOS using deuterated barrier-nitride processing

Deuterated barrier-nitride films and anneals in a deuterium ambient prior to first-metal have been incorporated into a conventional high-performance CMOS process and subjected to subsequent processing through five levels of metal. Device hot-electron stress results confirm that, even though some initial relaxation of the transistor lifetime improvement is observed with further hot processing, significant lifetime improvement can be achieved through full wafer processing through five levels of metal. The barrier-nitride acts as a reservoir for deuterium, maintaining high concentrations in the device regions through further processing. These results support the efficacy of using a deuterium reservoir to achieve a hot-electron hardened transistor.

Nitrided gate oxides for 3.3-V logic application: Reliability and device design considerations

Device characteristics and reliability in a 3.3-V logic CMOS technology with various gate oxidation and nitridation processes are described. The technology was designed to extend 3.3-V devices to the ultimate dielectric reliability limit while maintaining strict manufacturing cost control. A nitrided gate oxide provided the means to maintain hot-electron reliability at the level of the previous iteration, but at higher performance and lower processing cost. Conventional furnace processes in nitrous and nitric oxide, high-pressure oxidation in oxygen and nitrous oxide, and rapid-thermal processes using nitrous and nitric oxide were investigated. We found that the concomitant variations in fixed charge and thermal budget have a significant influence on both n-FET and p-FET device parameters such as threshold voltage, carrier mobility, and inverse short-channel effect (ISCE). Reliability effects, such as charge to breakdown (Q <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</inf> ), hot-electron degradation,and negative-bias temperature instability (NBTI) were examined and correlated with the nitrogen profile in the gate dielectric. Secondary ion mass spectroscopy (SIMS) profiles were used to characterize the oxidation techniques and to correlate gate dielectric composition to the parametric and reliability parameters.

On the correlation between drain-gate breakdown voltage and hot-electron reliability in InP HEMTs

By comparing devices with different recess widths, we show that the off-state drain-gate breakdown voltage (BV/sub DG/) may give totally misleading indications on the reliability of lattice-matched InP HEMTs under hot-electron (HE) and impact ionization conditions, from both standpoints of gradual and catastrophic degradation. Since the hot-electron degradation effects observed in our HEMTs are quite common, we believe that our results should be considered as a general caveat whenever indications on HE HEMT robustness are inferred from BV/sub DG/ measurements.

Analysis of hot-electron reliability and device performance in 80-nm double-gate SOI n-MOSFET's

In this paper, we employ a comprehensive Monte Carlo-based simulation method to model hot-electron injection, to predict induced device degradation, and to simulate and compare the performance of two double-gate fully depleted silicon-on-insulator n-MOSFET's (one with a lightly-doped channel and one with a heavily-doped channel) and a similar lightly-doped single-gate design. All three designs have an effective channel length of 80 nm and a silicon layer thickness of 25 mm. Monte Carlo simulations predict a spatial retardation between the locations of peak hot-electron injection into the front and back oxides. Since the observed shift is a significant portion of the channel length, the retardation effect greatly influences induced degradation in otherwise well-designed SOI devices. This effect may signal an important consideration for sub-100-nm design strategy. Simulations were also conducted to compare transistor performance against a key figure of merit. Evaluation of reliability and performance results indicate that the double-gate design with a lightly doped channel offers the best tradeoff in immunity to hot-electron-induced degradation and performance.