Hot Electron Induced Punch-through Research Articles

Hot-Electron-Induced Punch-Through (HEIP) Effect in p-MOSFET Enhanced by Mechanical Stress

Hot-carrier-induced degradation of short p-channel field-effect transistors in the presence of externally applied vertical mechanical force is investigated. The mechanical stress was induced in the devices by applying a normal load with a nanoindenter. Using finite element modeling, the induced stress to the channel was estimated to reach GPa range. It is shown that compressive mechanical stress considerably enhances the impact ionization rate and the generation of secondary electron-hole pairs. These can be trapped in the gate oxide and cause a hot-electron-induced punch-through effect and effective p-channel length reduction even after both mechanical and electrical stresses are removed. The presented findings indicate the importance of mechanical stress control and engineering for improving the device reliability.

Effect of reverse body bias on hot-electron-induced punchthrough reliability of pMOSFETs with thin gate dielectric at high temperatures

The effect of the reverse body bias VSB on the hot-electron-induced punch-through (HEIP) reliability of pMOSFETs with a thin gate dielectric at high temperatures was investigated for the first time. Experimental results indicate that the reverse VSB increased the HEIP degradation for a thin pMOSFET because of the increase in the maximum electric field Em due to the increase in the threshold voltage Vth. The sensitivity of HEIP degradation to VSB increased with increasing body effect coefficient γ at a given oxide thickness Tox. However, a thin device (22 Å) showed a much stronger dependence of HEIP degradation on VSB due to the decrease in the velocity saturation length l, although it had a smaller γ than a thick device (60 Å). These new observations suggest that the body bias technique for improving circuit performance can cause a reliability problem of nanoscale pMOSFETs at high temperatures and impose a significant limitation on CMOS device scaling.

Degradation in Pmosfet during Off-State Stress

Degradation of P-channel MOSFET during off-state stress with ac bias has been experimentally investigated. Sub-threshold leakage increased after off-state with ac bias. It was caused by hot electron injection during off-state. With varying source voltage, the degradation during off-state stress with ac bias was more severe than off-state stress with dc bias. Degradation impact was the same as hot electron induced punch-through (HEIP) during on-state. It was observed that subthreshold leakage current of pMOSFET increased and standby current became serious. Gate length, tap width, doping concentration at source/drain extension, operation temperature and operation frequency, respectively, were evaluated and the degradation modeling has been introduced in our paper. Figure 1

Degradation of pMOSFETs due to hot electron induced punchthrough

This paper proposes a method which can separate the parasitic effect from the drain current Id vs. gate voltage Vg curves of MOSFETs, then uses this method to analyze degradation of experimental pMOSFETs due to hot-electron-induced punchthrough (HEIP). An Id vs. Vg curve of the parasitic MOSFET formed by a shallow trench isolation (STI) is obtained by extrapolating the line of Id vs. channel width W at each Vg to W=0μm. The Id vs. Vg curves of the parasitic MOSFET indicate that HEIP caused electron trapping at the interface between SiN and the sidewall oxide of STI, but the curves of the main MOSFET indicate that HEIP caused negative oxide charges and positive interface traps in the channel region. These charges and traps decreased the threshold voltage Vth of the parasitic MOSFET but increased Vth of the main MOSFET. These two opposite behaviors of Vth resulted in little HEIP-induced shift of Vth at W=2.5μm. |Vd| to secure ten-year HEIP lifetime of 10% shift of Vth was ≤2.2V at W=0.3μm, ≤3.5V at W=1.0μm, and ≤3.6V at W=10μm; these changes indicate that degradation of parasitic MOSFET influences the HEIP lifetime of narrow pMOSFET significantly.

Separation of hot-carrier-induced interface trap creation and oxide charge trapping in PMOSFETs studied by hydrogen/deuterium isotope effect

By using the hydrogen/deuterium isotope effect, we propose a new technique to separate and quantify the effects of hot-carrier-induced interface trap creation and oxide charge trapping on the degradation in PMOSFETs. In addition to the well-known hot-electron-induced-punchthrough (HEIP) mechanism, we find that two additional mechanisms, namely, interface trap creation and hole trapping in the oxide, also play important roles in PMOSFET degradation. The degradation mechanisms are highly dependent on stress conditions. For low gate voltage V/sub gs/ stress, HEIP is found to dominate the shift of threshold voltage V/sub t/. When V/sub gs/ increases to a moderate value, the V/sub t/ shift can be fully dominated by interface trap creation. Hole injection and trapping into the oxide occurs when V/sub gs/ is increased further to V/sub gs/=V/sub ds/. For the first time, the effects of interface trap creation and oxide charge trapping on the V/sub t/ shift are quantified by the proposed technique.

Hot-electron-induced punchthrough (HEIP) effect in submicrometer PMOSFET's

Degradation of device characterisitics due to hot-carrier injection in submicrometer PMOSFET has been investigated. We found that in submicrometer p-channel transistors the punchthrough voltage is seriously reduced due to hot-electon-induced punchthrough (HEIP). A worst case analysis of the experimental data shows substantially reduced lifetime due to HEIP.