Host-network Interface Research Articles

Adaptable Switch: A Heterogeneous Switch Architecture for Network-Centric Computing

Network-centric computing offloads and disaggregates computing and data processing from CPU to network in order to support growing throughput, big data volume, and information complexity in data centers. An emerging paradigm is employing SmartNIC for network-centric computing, which introduces user-specific processing at a host's network interface. In this article, we take this initiative further to tackle current proprietary processing and computing issues in the network core: the switches. We propose a new hardware architecture called adaptable switch. Based on testing of its prototype empowering three use cases, we demonstrate that both high throughput and processing flexibility can be achieved simultaneously on an adaptable switch.

(Invited) Silica Based Ionogels: Raman Study of Protic Vs. non Protic Ionic Liquids, with Lithium Salt Vs. Sodium Salt

Ionogels represent a route to biphasic materials, for the use of ionic liquids (ILs) for all solid devices. Confining ILs within host networks enhances their averaged dynamics, resulting in improved charge transport. Fragility, short relaxation times, low viscosity, and good ionic conductivity, all them appear to be related to the IL / host network interface. The presence of ILs at interface neighborhood leads to the lowering of cation-anion interaction, i.e. to the breakdown of aggregated and structured regions that are systematically found in bulk ILs.[1] This “destructuration”, as well as segregative interactions at interface,[2] coupled with percolation of the bicontinuous solid/liquid interface,[3] make these materials very competitive among the existing solid electrolytes.Herein we will present an in-depth study of coordination of TFSI anion with lithium or with sodium cations, in the presence of protic or non protic pyrrolidinium cations, confined within silica with well-controlled porosities. The coordination number of TFSI-cation is shown to decrease upon confinement, making the lithium of sodium cation more diffusive. Moreover, the cation-anion layering at the interface is studied by DFT and shows striking modifications when a lithium or sodium salt is added, thus highlighting the effect of the chemistry of the host network, similarly with previous study.[4] References 1) A. Guyomard-Lack, P.-E. Delannoy, N. Dupré, C. V. Cerclier, B. Humbert, J. Le Bideau, Phys. Chem. Chem. Phys., 16, (2014) 23639-236452) A. Guyomard-Lack, B. Said, N. Dupré, A. Galarneau, J. Le Bideau, New J. Chem., 40, (2016) 4269-42763) C. V. Cerclier, J.-M. Zanotti, J. Le Bideau, Phys. Chem. Chem. Phys., 17, (2015) 29707—297134) D. Aidoud, D. Guy-Buissou, D. Guyomard, B. Lestriez, J. Le Bideau, J. Electrochem. Soc., 165, (2018) A3179-A3185

Minimizing the usage of hardware counters for collective communication using triggered operations

Triggered operations and counting events or counters are building blocks used by communication libraries, such as MPI, to offload collective operations to the Host Fabric Interface (HFI) or Network Interface Card (NIC). Triggered operations can be used to schedule a network or arithmetic operation to occur in the future, when a trigger counter reaches a specified threshold. On completion of the operation, the value of a completion counter increases by one. With this mechanism, it is possible to create a chain of dependent operations, so that the execution of an operation is triggered when all the operations it depends on have completed its execution.Triggered operations rely on hardware counters on the HFI and are a limited resource. Thus, if the number of required counters exceeds the number of hardware counters, a collective needs to stall until a previous collective completes and counters are released. In addition, if the HFI has a counter cache, utilizing a large number of counters can cause cache thrashing and provide poor performance. Therefore, it is important to reduce the number of counters, especially when running on a large supercomputer or when an application uses non-blocking collectives and multiple collectives can run concurrently. Moreover, counters being a scarce resource, it is important for the MPI library to be able to estimate the number of counters required by a collective so that it can fallback to the software implementation when the number of available counters is less than the required number.In this paper, we propose an algorithm to optimize the number of hardware counters used when offloading collectives with triggered operations. With our algorithm, different operations can share and re-use trigger and completion counters based on the dependences among them and their topological orderings. We have also proposed models to estimate the number of counters required by different collectives when using the optimization algorithm. While the proposed counter optimization algorithm assumes that the dependences among various operations in a collective are represented using a Directed Acyclic Graph (DAG), there might be cases when no DAGs are provided for the collective. In this paper, we also discuss how we can optimize the usage of counters for such cases. Our experimental results show that our proposed algorithm significantly reduces the number of counters over a naïve approach that does not consider the dependences among the operations.

Photo-polymerized organic host network of ionogels for lithium batteries: effects of mesh size and of ethylene oxide content

Ionogels represent a route to biphasic materials, for the use of ionic liquids (ILs) for all-solid devices. Confining ILs within host networks enhances their averaged dynamics, resulting in improved charge transport. Fragility, short relaxation times, low viscosity, and good ionic conductivity, all them appear to be related to the IL / host network interface. The presence of ILs at interface neighborhood leads to the breakdown of aggregated, structured regions that are systematically found in bulk ILs. This “destructuration”,1 as well as segregative interactions at interface,2 coupled with percolation of the bicontinuous solid/liquid interface,3 make these materials very competitive among the existing solid electrolytes. Such approach could provide (i) a route to lower locally the viscosity of ILs, and (ii) an easier pathway for diffusion of charged species. Several types of ionogels demonstrate this effect, taking into account of fully inorganic, hybrid, polymeric or organic-inorganic host networks . This “all solid” approach can be applied to several electrochemical energy storage sources, including lithium batteries 2,4 and supercapacitors.5 Herein we will emphasize the results of systematic studies of the effect of size of confinement, either within pores of solids or within meshes of polymers.2,6 Besides the effect of the size of the confinement, the chemical nature of the host network is investigated. Several examples showed that the best properties were obtained on the basis of a good balance between features of host network and features of confined ionic liquid.

(Invited) Ionogels for Safer Energy Storage: The Determining Effect of the Interface

Ionogels represent a route to biphasic materials, for the use of ionic liquids (ILs) for all-solid devices. Confining ILs within host networks enhances their averaged dynamics, resulting in improved charge transport. Fragility, short relaxation times, low viscosity, and good ionic conductivity, all them appear to be related to the IL / host network interface. The presence of ILs at interface neighborhood leads to the breakdown of aggregated, structured regions that are systematically found in bulk ILs. This “destructuration”,1 as well as segregative interactions at interface,2 coupled with percolation of the bicontinuous solid/liquid interface,3 make these materials very competitive among the existing solid electrolytes. Such approach could provide (i) a route to lower locally the viscosity of ILs, and (ii) an easier pathway for diffusion of charged species. Several types of ionogels demonstrate this effect, taking into account of fully inorganic, hybrid, polymeric or organic-inorganic host networks . This “all-solid” approach can be applied to several electrochemical energy storage sources, including lithium batteries (Fig 1)2,4 and supercapacitors (Fig. 2).5 Strikingly, high performance were shown on these devices, thanks to interfacial effects of confined ILs, with sometimes heightened properties of the chosen ILs as referred to their bulk properties.2,3,6 Such solid electrolytes are particularly well suited for microdevices that we have been or are being developed (Fig. 3).5,6 Herein we will emphasize the results of a systematic study of the effect of size of confinement.

Ionogels for Safer Energy Storage: The Determining Effect of the Interface

Ionogels represent a route to biphasic materials, for the use of ionic liquids (ILs) for all-solid devices. Confining ILs within host networks enhances their averaged dynamics, resulting in improved charge transport. Fragility, short relaxation times, low viscosity, and good ionic conductivity, all them appear to be related to the IL / host network interface. The presence of ILs at interface neighborhood leads to the breakdown of aggregated, structured regions that are systematically found in bulk ILs. This “destructuration”,[1] as well as segregative interactions at interface,[2,3] coupled with percolation of the bicontinuous solid/liquid interface,[4] make these materials very competitive among the existing solid electrolytes. Such approach could provide (i) a route to lower locally the viscosity of ILs, and (ii) an easier pathway for diffusion of charged species. Several types of ionogels demonstrate this effect, taking into account of fully inorganic, hybrid, polymeric or organic-inorganic host networks . This “all-solid” approach can be applied to several electrochemical energy storage sources, including lithium batteries (Fig 1)[3,5] and supercapacitors (Fig. 2)[6,7]. Strikingly, high performance were shown on these devices, thanks to interfacial effects of confined ILs, with sometimes heightened properties of the chosen ILs as referred to their bulk properties[3,4,7,8]. Such solid electrolytes are particularly well suited for microdevices that we have been or are being developed (Fig. 3)[6,9]. Herein we will emphasize the results of a systematic study of the effect of size of confinement.

Development of a Flexible Real-Time Monitor for an Enterprise Network

paper presents the design and implementation of a technique that can be used in a real-time network monitoring. It provides a Real-Time Network Monitoring System (RTNMS) that allows a host to capture any packets in a network by putting the host's Network Interface Card (NIC) into the promiscuous mode. Modular design has been devised. RTNMS consists of five modules that are integrated to give the required features. These features automatically give system administrators a helping hand in management and fault detection on a network. RTNMS is user-friendly because it has been augmented by a user interface to assist in navigating the capture and analysis of packets. It can be tapped into an enterprise network with high flexibility. It can significantly increase the efficiency of data capture and network monitoring through the association of various modules.

Eager Data Transfer Mechanism for Reducing Communication Latency in User-Level Network Protocols

Abstract: Clusters have become a popular alternative for building high-performance parallel computing systems. Today’s high-performance system area network (SAN) protocols such as VIA and IBA significantly reduce user-to-user communication latency by implementing protocol stacks outside of operating system kernel. However, emerging parallel applications require a significant improvement in communication latency. Since the time required for transferring data between host memory and network interface (NI) make up a large portion of overall communication latency, the reduction of data transfer time is crucial for achieving low-latency communication. In this paper, Eager Data Transfer (EDT) mechanism is proposed to reduce the time for data transfers between the host and network interface. The EDT employs cache coherence interface hardware to directly transfer data between the host and NI. An EDT-based network interface was modeled and simulated on the Linux-based, complete system simulation environment, Linux/SimOS. Our simulation results show that the EDT approach significantly reduces the data transfer time compared to DMA-based approaches. The EDT-based NI attains 17% to 38% reduction in user-to-user message time compared to the cache-coherent DMA-based NIs for a range of message sizes (64 bytes ~ 4 Kbytes) in a SAN environment.

A scalable, commodity data center network architecture

Today's data centers may contain tens of thousands of computers with significant aggregate bandwidth requirements. The network architecture typically consists of a tree of routing and switching elements with progressively more specialized and expensive equipment moving up the network hierarchy. Unfortunately, even when deploying the highest-end IP switches/routers, resulting topologies may only support 50% of the aggregate bandwidth available at the edge of the network, while still incurring tremendous cost. Non-uniform bandwidth among data center nodes complicates application design and limits overall system performance.In this paper, we show how to leverage largely commodity Ethernet switches to support the full aggregate bandwidth of clusters consisting of tens of thousands of elements. Similar to how clusters of commodity computers have largely replaced more specialized SMPs and MPPs, we argue that appropriately architected and interconnected commodity switches may deliver more performance at less cost than available from today's higher-end solutions. Our approach requires no modifications to the end host network interface, operating system, or applications; critically, it is fully backward compatible with Ethernet, IP, and TCP.

An Embedded RISC Core Performance for ATM Network Interface Processing

The use of an embedded reduced instruction set computer (RISC) as a processing core for an ATM network interface can provide such interface with very useful features, such as simplicity of interface design, short developing cycle, and reduced cost of development. In addition, it provides scalability where such core could support the processing requirements by ATM interface to deliver different high-speed data transmission, which the user-network ATM interface protocol recommends. This article describes a VHDL-based simulation study we have conducted to investigate the RISC core design issues for high-speed scalable ATM host-network interface. The simulation results have shown that the three-stage pipeline RISC core supported with forwarding mechanism and delayed branch technique can process all the ATM interface codes without performance penalty due to the read-after-write data hazards and conditional branch processing. The core should be supported, however, with a forwarding mechanism to eliminate the stalling of the pipeline due to the processing of the conditional branch instructions. Also, the core structure should include a content addressable memory and direct memory access and support a simple instruction set. Also, the results show that a cost-effective RISC core could support a wide range of ATM user-network speeds.

Implementing network protocols at user level

Traditionally, network software has been structured in a monolithic fashion with all protocol stacks executing either within the kernel or in a single trusted user-level server. This organization is motivated by performance and security concerns. However, considerations of code maintenance, ease of debugging, customization, and the simultaneous existence of multiple protocols argue for separating the implementations into more manageable user-level libraries of protocols. This paper describes the design and implementation of transport protocols as user-level libraries.We begin by motivating the need for protocol implementations as user-level libraries and placing our approach in the context of previous work. We then describe our alternative to monolithic protocol organization, which has been implemented on Mach workstations connected not only to traditional Ethernet, but also to a more modern network, the DEC SRC ANI. Based on our experience, we discuss the implications for host-network interface design and for overall system structure to support efficient user-level implementations of network protocols.

The architecture and implementation of a high-speed host interface

In the design of a high-speed network, the host network interface is a critical component in achieving high end-to-end throughput. Some of the architectural issues involved in host interfacing are discussed. These include the appropriate partitioning of functionality between host and interface and the choice of mechanism for data movement into, out of, and within the host. The general issues are considered in a specific example: the realization of a highly flexible host interface for a 622-Mb/s asynchronous transfer mode network. The architecture of such an interface is described, and the experimental results obtained from its prototype implementation are presented. The prototype will allow experimentation with a variety of scheduling and segmentation/reassembly algorithms, and with new transport protocols, while also delivering high bandwidths to the host.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Design of a Gigabit Host-Network Interface

We have proposed a new architecture called Axon that meets the challenges of delivering high network bandwidth directly to applications. Its novel aspects include: an integrated design of host and network interface hardware, operating systems, and communication protocols; the proper division of hardware and software function; reorganisation of end-to-end protocols to take advantage of the increased functionality of the emerging high speed internetworks; and a pipelined interface between the network and host memory with no packet buffering.The pipelined network interface performs critical per packet processing in hardware as packets flow through the pipeline, without imposing any store-and-forward buffering of packets. This requires the design of error and flow control mechanisms to be simple enough for implementation in the network interface hardware, while providing the functionality required by applications.This paper describes the design of the host-network interface, and, in particular, the hardware design of the critical per packet processing with emphasis on error and flow control. An extensive simulation model of the network interface hardware has been used to determine the feasibility and performance of hardware implementation of these functions.

Implementing network protocols at user level

Traditionally, network software has been structured in a monolithic fashion with all protocol stacks executing either within the kernel or in a single trusted user-level server. This organization is motivated by performance and security concerns. However, considerations of code maintenance, ease of debugging, customization, and the simultaneous existence of multiple protocols argue for separating the implementations into more manageable user-level libraries of protocols. The present paper describes the design and implementation of transport protocols as user-level libraries. The authors begin by motivating the need for protocol implementations as user-level libraries and placing their approach in the context of previous work. They then describe their alternative to monolithic protocol organization, which has been implemented on Mach workstations connected not only to traditional Ethernet, but also to a more modern network, the DEC SRC AN1. Based on the authors' experience, they discuss the implications for host-network interface design and for overall system structure to support efficient user-level implementations of network protocols.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Gigabit networking research at Bellcore

A communication architecture appropriate for gigabit networks, the multimedia end-to-end communication architecture (MECA), is described. MECA provides multimedia applications with the service they require in a single communication system. MECA encompasses the network, host-network interface, and associated protocols. The architectural characteristics of MECA are compared with those of existing communication systems and the TP++ transport protocol used by MECA is compared to existing transport protocols. Three host-network interfaces built for AURORA, a five-gigabit testbed network that includes an experimental asynchronous transfer mode (ATM) network running over a synchronous optical network (SONET), are described. The Sunshine ATM switch that supports MECA using a scalable Batcher-Banyan switching fabric and highly programmable port controllers is discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A host-network interface architecture for ATM

A host-network interface architecture for ATM

Performance evaluation of communication protocols for distributed processing

The overhead introduced by communications software significantly impacts the performance of most distributed applications. To derive the optimum performance from a distributed application and to determine areas for improvement in new communication protocols, it is essential to identify the factors that affect communication delay. This paper examines two factors that affect the performance of communication protocols: the granularity of communication and traffic at a host's network interface. Three transport mechanisms, the Transmission Control Protocol, the User Data Protocol, and DECnet, utilizing an Ethernet local area network are considered. Results are reported for an experimental study using a dedicated network monitor. The results demonstrate the influence of these two factors on communication protocols. Based on results for UDP and DECnet, models for estimating delay are presented. Suggestions are also made for the improvement of future transport protocols and for methods to reduce communication delay in distributed applications.