Horizontal Architectures Research Articles

(Invited) Impact of Processing Factors on the Low-Frequency Noise of Gate-All-Around Silicon Vertical Nanowire FETs

Future CMOS technology nodes will rely on Gate-All-Around (GAA) FETs with ultimate control over the short-channel effects. In this class of devices, GAA Vertical Nanowires (VNWs) offer some clear integration advantages over horizontal architectures. In addition, some operational parameters are also favourable, like, the low-frequency (LF) noise, as shown recently [1]-[3]. In this work, an overview will be given of the impact of certain processing factors on the noise spectrum and magnitude of silicon GAA VNW FETs.Silicon NWs with a diameter of ~45 (50) nm have been epitaxially grown on either bulk or Silicon-On-Insulator (SOI) substrates. They are either undoped (intrinsic) or in-situ B/P-doped (p/nMOS), resulting in the latter case in a Junctionless (JL) structure. For the “bulk” devices an in-situ B-doped (or P-doped) silicon back contact has been deposited as source electrode, while an in-situ B-doped SiGe source was grown on SOI (pFETs). In both cases, a highly B-doped SiGe (or P-doped silicon) drain was deposited on the 90 nm long NWs to reduce the series resistance. LF noise measurements have been performed as described elsewhere [1],[2], in linear operation (|VDS|=0.05 mV), for a current range from about 10 nA to a few mA. Spectra have been recorded in Forward (F) mode or in Reverse (R) mode, with source and drain switched.The impact of the width of the RMG cap, shown in Fig. 1 on the F noise of GAA VNW nFETs has been reported before [1], showing that the use of a wide cap results in a lower input-referred voltage noise PSD (SVG) (Fig. 2). The asymmetry in SVG at f=10 Hz in F and R operation of GAA VNW pFETs is represented in Fig. 3 (bulk source) and Fig. 4 (SOI). While significantly lower noise is observed in R operation for “bulk”, insignificant differences are seen for the SOI pFETs. At the same time, the PSD is generally lower for the bottom source (bulk) compared with a SiGe source on SOI (Fig. 5). More detailed analysis reveals that the 1/f noise is dominated by mobility fluctuations (Dm) for VNW pFETs on bulk substrates [2]. The situation is more complicated for SOI pFETs a shown in Fig. 6 and depends on the channel doping density. In weak inversion (low ID), either Dn or Dm fluctuations can prevail. At higher ID, access resistance (RS) starts to dominate the 1/f noise behaviour. Finally, also the in-situ B doping density plays a significant role in the LF noise mechanism of the JL channels (Fig. 6), offering several technology knobs to optimize the 1/f noise performance.[1] E. Simoen, A. Chasin, P. Matagne, E. Rosseel, A. Hikavyy, R. Loo, P. Favia, H. Bender, E. Vancoille and A. Veloso, ECS Trans., 97 (5), pp. 59-64 (2020).[2] E. Simoen et al., submitted to Solid-State Electron.[3] T. Imamoto, Y. Ma, M. Muraguchi and T. Endoh, Jpn. J. Appl. Phys., 54, p. 04DC11 (2015). Figure 1

Tackling Critical Challenges towards Efficient CyberPhysical Components & Services Interconnection: The ATLAS CPS Platform Approach

Cyber-Physical Systems (CPS) comprise a rapidly expanding research domain incorporating various diverse ICT aspects. Consequently, such systems are characterized by high degree of heterogeneity regarding communication, hardware and software technologies. Additionally, a high number of challenges must be tackled before such horizontal architectures can yield useful services, that can be exploited by todays and future consumer electronics and respective vertical domains. Aiming to address such objectives, this paper proposes a holistic end-to-end CPS architecture based on message passing communication technologies able to support the inherent complexity of respective deployments spanning several areas of applied industrial research and development. In this context, this paper aims to serve as a roadmap on how existing, prominent technologies from different domains can be effectively integrated and address all changes while be applied in diverse application demands. This is achieved by analytically presenting the proposed ATLAS infrastructure emphasizing on integration of prominent consumer electronics technologies. Finally, the deployment of the proposed solution in different verticals is presented, highlighting i) the applicability of the system and ii) a resource conservative behavior advocating the integration with nowadays COTS embedded systems.

Performance-Enhanced Caching Scheme for Web Clusters for Dynamic Content

In order to improve the QoS of applications, clusters of web servers are increasingly used in web services. Caching helps improve performance in web servers, but is largely exploited only for static web content. With more web applications using backend databases today, caching of dynamic content has a crucial role in web performance. This paper presents a set of cache management schemes for handling dynamic data in web clusters by sharing cached contents. These schemes use either automatic or expiry-based cache validation, and work with any type of request distribution. The techniques improve response by utilizing the caches efficiently and reducing redundant database accesses by web servers while ensuring cache consistency. The authors present caching schemes for both horizontal and vertical cluster architectures. Simulations show an appreciable performance rise in response times of queries in clustered web servers.

Network Design in Games with Spillovers

How should an organization be designed in order to provide its members with minimal incentives to defect? And how does the optimal design depend on the type of strategic interaction between defectors and remaining organizational members? This paper addresses such issues in a game theoretic model of cooperation, in which an organization is formally represented by a connected network, and where gains from cooperation are given by a partition function. We show that critical structural features of the organization depend in a clear-cut way on the sign of spillovers. In particular, positive spillovers favor the adoption of dispersed and centralized forms, while negative spillovers favor cohesive and horizontal ones. Moreover, if the organizational form determines all the communication possibilities of members, a highly centralized organization - the star - emerges under positive spillovers, whereas two horizontal architectures - the circle and the complete - emerge under negative spillovers.

Network design in games with spillovers

How should an organization be designed in order to provide its members with minimal incentives to defect? And how does the optimal design depend on the type of strategic interaction between defectors and remaining organizational members? This paper addresses such issues in a game theoretic model of cooperation, in which an organization is formally represented by a connected network, and where gains from cooperation are given by a partition function. We show that critical structural features of the organization depend in a clear-cut way on the sign of spillovers. In particular, positive spillovers favor the adoption of dispersed and centralized forms, while negative spillovers favor cohesive and horizontal ones. Moreover, if the organizational form determines all the communication possibilities of members, a highly centralized organization—the star—emerges under positive spillovers, whereas two horizontal architectures—the circle and the complete—emerge under negative spillovers.

Software tools in context

A context is provided for understanding where tools fit in the software life cycle. Tools are divided into vertical and horizontal architectures. Vertical tools support specific activities in a single life-cycle phase, such as analysis, design, or testing. Horizontal tools support activities across the entire life cycle, such as project management and cost estimation. The task of tool integration is described. Trends and anticipated changes for the next few years are covered.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Tradeoffs in instruction format design for horizontal architectures

With recent improvements in software techniques and the enhanced level of fine grain parallelism made available by such techniques, there has been an increased interest in horizontal architectures and large instruction words that are capable of issuing more that one operation per instruction. This paper investigates some issues in the design of such instruction formats. We study how the choice of an instruction format is influenced by factors such as the degree of pipelining and the instruction's view of the register file. Our results suggest that very large instruction words capable of issuing one operation to each functional unit resource in a horizontal architecture may be overkill. Restricted instruction formats with limited operation issuing capabilities are capable of providing similar performance (measured by the total number of time steps) with significantly less hardware in many cases.

A microprogramming logic

A universal syntax-directed proof system is presented for the verification of horizontal computer architectures. The system is based on the axiomatic architecture description language AADL, which is sufficiently rich to allow the specification of target architectures while providing a concise model for clocked microarchitectures. For each description A epsilon AADL of a host, it is shown how to construct systematically a (Hoare-style) axiomatic definition of an A-dependent high-level microprogramming language based on S*. The axiomatization of A's microoperations together with a powerful proof-rule dealing with the inherent low-level parallelism of horizontal architectures allow a complete axiomatic treatment of the timing behavior and dynamic conflicts of microprograms written in S*(A).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An axiomatization of low-level parallelism in microarchitectures

This paper presents the heart of a universal syntax-directed proof system for the verification of horizontal computer architectures. The system is based on the axiomatic architecture description language AADL, which incorporates a comcise model of clocked microarchitectures. For a given description A of a host architecture, we show how to axiomatize A's microoperations and present powerful proof-rules dealing with the inherent low-level parallelism of horizontal architectures. They allow for a complete axiomatic treatment of the timing behaviour and dynamic conflicts of microprograms written in an A-dependent high-level microprogramming language based on S*.

Architectural support for the efficient generation of code for horizontal architectures

Horizontal architectures, such as the CDC Advanced Flexible Processor [I] and the FPS APi20-B [2}, consist of a number of resources that can operate in parallel, each of which is controlled by a field in the wide instruction word. Such architectures have been developed to perform high speed scientific computations at a modest cost: Figure 1 displays those characteristics of horizontal architectures that are germane to the issues discussed in this paper. The simultaneous requirements of high performance and low cost lead to an architecture consisting of multiple pipelined processing elements (PEs) such as adders and multipliers, a memory (which for scheduling purposes may be viewed as yet another PE with two operations: a READ and a WRITE), and an interconnect which ties them all together. The interconnect allows the result of one operation to be directly routed to another PE as one of the inputs for an operation that is to be performed there. The required memory bandwidth is reduced since temporary values need not be written to and read from the memory. The final aspect of horizontal processors that is of interest is that their program memories emit wide instructions which synchronously specify the actions of the multiple and possibly dissimilar PEs. The program memory is sequenced by a conventional sequencer that assumes sequential flow of control unless a branch is explicitly specified. As a consequence of the simplicity of such an architecture, it is inexpensive relative to the potential performance of the multiple pipelined PEs. However, if this potential performance is to be realized, the multiple resources of a horizontal processor must be scheduled effectively. The scheduling task for conventional horizontal processors is quite complex and the construction of highly optimizing compilers for them is a difficult and expensiw3 project. The polycyclic architecture [3- 6] is a horizontal architecture with architectural support for the scheduling task. The cause of the complexity involved in scheduling conventional horizontal processors and the manner in which the polycyclic architecture addresses this issue are outlined in this paper.

Architectural support for the efficient generation of code for horizontal architectures

Horizontal architectures, such as the CDC Advanced Flexible Processor [I] and the FPS APi20-B [2}, consist of a number of resources that can operate in parallel, each of which is controlled by a field in the wide instruction word. Such architectures have been developed to perform high speed scientific computations at a modest cost: Figure 1 displays those characteristics of horizontal architectures that are germane to the issues discussed in this paper. The simultaneous requirements of high performance and low cost lead to an architecture consisting of multiple pipelined processing elements (PEs) such as adders and multipliers, a memory (which for scheduling purposes may be viewed as yet another PE with two operations: a READ and a WRITE), and an interconnect which ties them all together. The interconnect allows the result of one operation to be directly routed to another PE as one of the inputs for an operation that is to be performed there. The required memory bandwidth is reduced since temporary values need not be written to and read from the memory. The final aspect of horizontal processors that is of interest is that their program memories emit wide instructions which synchronously specify the actions of the multiple and possibly dissimilar PEs. The program memory is sequenced by a conventional sequencer that assumes sequential flow of control unless a branch is explicitly specified. As a consequence of the simplicity of such an architecture, it is inexpensive relative to the potential performance of the multiple pipelined PEs. However, if this potential performance is to be realized, the multiple resources of a horizontal processor must be scheduled effectively. The scheduling task for conventional horizontal processors is quite complex and the construction of highly optimizing compilers for them is a difficult and expensiw3 project. The polycyclic architecture [3- 6] is a horizontal architecture with architectural support for the scheduling task. The cause of the complexity involved in scheduling conventional horizontal processors and the manner in which the polycyclic architecture addresses this issue are outlined in this paper.

Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing

Horizontal architectures are attractive for cost-effective, high performance scientific computing. They are, however, very difficult to schedule. Consequently, it is difficult to develop compilers that can generate efficient code for such architectures. The polycyclic architecture has been developed specifically to make the task of scheduling easy. As a result, it has been possible to develop a powerful scheduling algorithm that yields optimal and near-optimal schedules for iterative computations. This novel architecture and this scheduling algorithm are the topic of this paper.