High-density Wiring Research Articles

Flexible Superconducting Wiring for Integration with Low-Temperature Detector and Readout Fabrication

We present a method of creating high-density superconducting flexible wiring on flexible thin silicon substrates. The flexible wiring, called SOI flex, is created by depositing superconducting wiring on a silicon-on-insulator (SOI) wafer, selectively etching away the thicker silicon section handle layer, and bending the thinner silicon device layer. We show measurements of superconducting transition temperature and critical current for Mo, Nb, and Al on SOI flex. We discuss the expected advantages of SOI flex for low-temperature detector applications, as well as the role of stress and strain in bent silicon and niobium.

Digital twin driven intelligent manufacturing for FPCB etching production line

Flexible printed circuit board (FPCB) exhibits high wiring density and good bendability to be widely used in smart devices. Traditional FPCB etching production lines are mostly discrete manufacturing workshops, which need to be upgraded with intelligence to meet the production requirements of high precision, production efficiency, and product yield. As an emerging technology, the digital twin can achieve the interoperability between physical and digital worlds of manufacturing systems. In this study, a digital twin driven FPCB etching intelligent production line is design. Data service system obtains comprehensive data from the production line in real time and provides intelligent data services. Real time mapping and online control system accomplishes the real time mapping and closed-loop control of intelligent production line. Key process databases are established to obtain optimal process parameters by analyzing the key processes of FPCB etching intelligent production line. The result shows that the process parameters of production line can be updated and adjusted accurately in real time to ensure good consistency and reliability of products. Currently, the FPCB etching intelligent production line can achieve the line forming at the minimum 16 μm line pitch and significantly improve the product yield.

High-Density Wire Formations by High-Resolution Printed Electronics

High-Density Wire Formations by High-Resolution Printed Electronics

Optimized chemical mechanical polishing of Parylene C for high-density wiring in flexible electronics

With the rapid development of flexible electronics, an increasing number of microfabrication strategies originating from the Si-based integrated circuits field have been explored on organic materials. Parylene C, a polymer, has been widely used in the microelectromechanical systems field because of its outstanding fabrication merits, such as room-temperature processability, conformal coating, and precise thin film deposition capability with the thickness tunable from 1 nm to 100 μm. As a good dielectric material, the Parylene C is also suitable for interlayer dielectrics in flexible electronics. This study develops an optimized chemical mechanical polishing (CMP) technique of Parylene C for high-density redistribution wiring in high-performance flexible electronics. The roughness of the Parylene C surface after CMP was as low as 14.3 ± 1.5 Å. The problems of slurry pollution and mechanical failure of the Parylene film that degrade the dielectric performance of the Parylene C could be avoided by taking the optimized CMP method. The multi-material structure constructed by Parylene C, Silicon and electroplated Copper was prepared and polished using the optimized CMP process. Additionally, a flexible wiring sample has been successfully patterned by the Damascene process through the optimized CMP process. In this sample, both the distance between each wire and the wire width were as small as 5 μm. The optimized Parylene C CMP process is easy-to-realize, highly efficient, low cost, and with minor defects; it provides a promising way to achieve high-density interconnection in high-performance flexible electronic devices.

Design and Optimization Methods of the Header of HDI PCB Rogowski Current Sensors

Printed circuit board (PCB)-based headers of Rogowski current sensors (HRCSs) have garnered growing interest from researchers in recent years, and they have been widely applied in many electrical scenarios due to their advanced features, such as nondeformable volume, flexible shape and size, and low cost. The determination of PCB HRCS parameters mainly depends on a time-consuming finite-element simulation, but these simulations cannot be used to calculate PCB HRCSs with a complex irregular structure or high-density thin winding wire. This article presents a method to calculate a PCB HRCS to address complex irregular structures and high-density thin winding wire. Furthermore, because it does not involve the time-consuming meshing process, this method is relatively fast. Taking two HRCSs with a given complex structure and thin winding wire as examples, we used the proposed method to determine its sensitivity, anti-interference characteristics, and the influence of the obtained internal parasitic capacitance and inductance parameters on the measured output voltage. Moreover, the optimal structural parameters of these PCB HRCSs are discussed when the installation space and the cross section of the measured conductor are given. The results of the high-density PCB HRCS experiments verify the proposed method.

High-Throughput Nanoparticle Chemisorption Printing of Chemical Sensors with High-Wiring-Density Electrodes

We report on the high-throughput non-lithographic microprinting of a high-wiring-density interdigitated array electrode (line and space = 5 µm/5 µm), based on a facile wet/dewet patterning of silver nanoparticle ink. The trade-off between high-density wiring and pattern collapse in the wet/dewet patterning is overcome by employing a new herringbone design of interdigitated array electrode. We demonstrate electrochemical sensing of p-benzoquinone by the fabricated interdigitated array electrode, showing a typical steady-state I–V characteristics with superior signal amplification benefiting from the redox cycling effect. Our findings provide a new technical solution for the scalable manufacture of advanced chemical sensors, with an economy of scale that cannot be realized by other techniques.

Practical Design Methodology of Mode-Conversion-Free Tightly Coupled Asymmetrically Tapered Bend for High-Density Differential Wiring

Practical Design Methodology of Mode-Conversion-Free Tightly Coupled Asymmetrically Tapered Bend for High-Density Differential Wiring

Investigation on Chemical Etching Process of FPCB With 18 μm Line Pitch

Flexible printed circuit boards (FPCB) are widely used in smart devices with high wiring density and light weight. In this paper, the chemical etching process of FPCB with 18 $\mu \text{m}$ line pitch is investigated. A geometric model of the FPCB circuit with the shape of “T” is established and simulated by the finite element method. The time evolution of the etching cavity, concentration field and velocity field of CuCl2 solution are studied, as well as the effects of initial concentrations and inlet velocities on the etching cavity profile. Finally, the FPCB sample with 18 $\mu \text{m}$ line pitch is successfully fabricated by employing process parameters from the etching simulation. The results show that as the increase in the etching cavity, recirculating eddies form at the bottom of the photoresist in the corners of the etching cavity, resulting in more etching on the top sides of sidewalls over time. Higher initial concentration of the etching solution will result in a larger etching cavity profile, but the inlet velocity cannot affect the etching cavity profile significantly. Finally, the effectiveness of the simulation model is verified by comparing the etching cavity profiles with four experiments.

The drift chamber of the MEG II experiment

The MEG experiment at the Paul Scherrer Institut searches for the charged-Lepton-Flavor-Violating μ+→ e+γ decay. MEG has already set the world best upper limit on the branching ratio: BR<4.2×10−13 @ 90% C.l. An upgrade (MEG II) of the whole detector has been approved to obtain a substantial increase of sensitivity. Currently MEG II is completing the upgrade of the various detectors, an engineering run and a pre-commissioning run were carried out during 2018 and 2019. The new positron tracker is a unique volume, ultra-light He based cylindrical drift chamber (CDCH), with high granularity: 9 layers of 192 square drift cells, ∼6–9 mm wide, consist of ∼12000 wires in a full stereo configuration. To ensure the electrostatic stability of the drift cells a new wiring strategy should be developed due to the high wire density (12 wires/cm2), the stringent precision requirements on the wire position and uniformity of the wire mechanical tension (better than 0.5 g). The basic idea is to create multiwire frames, by soldering a set of (16 or 32) wires on 40 μm thick custom wire-PCBs. Multiwire frames and PEEK spacers are overlapped alternately along the radius, to set the proper cell width, in each of the twelve sectors defined by the spokes of the rudder wheel shaped end-plates. Despite to the conceptual simplicity of the assembling strategies, the building of the multiwire frames, with the set requirements, imposes a use of an automatic wiring system. The MEG II CDCH is the first cylindrical drift chamber ever designed and built in a modular way and it will allow to track positrons, with a momentum greater than 45 MeV/c, with high efficiency by using a very small amount of material, 1.5x10−3 X0. We describe the CDCH design and construction, the wiring phase at INFN-Lecce, the choice of the wires, their mechanical properties, the assembly and sealing at INFN-Pisa and the preliminary commissioning activities at PSI.

Microwave engineering for semiconductor quantum dots in a cQED architecture

We develop an engineered microwave environment for coupling high Q superconducting resonators to quantum dots using a multilayer fabrication stack for dot control wiring. Analytical and numerical models are presented, which show that high resonator quality factors can be attained by either minimizing the parasitic coupling capacitance to the leads or creating a low effective environmental impedance at the cavity frequency. We implement the later approach by fabricating low characteristic impedance (Zg≈10 Ω) microstrips on-chip for the dot bias wiring and show resonator quality factors of 8140 that can be attained without the addition of explicit filtering. Using this approach, we demonstrate single electron occupation in double and triple dots detected via dipole or quadrupole coupling to a superconducting resonator. Additionally, by using multilayer fabrication, we are able to improve ground plane integrity and keep microwave crosstalk below −20 dB out to 18 GHz while maintaining high wire density, which will be necessary for future circuit quantum electrodynamics quantum dot processors.

Construction of amorphous Ni(OH)2@nickel nanowire with interconnected structure as advanced core-shell electrodes for asymmetric supercapacitors

Abstract Amorphous Ni(OH)2 closely coating on interconnected nickel nanowire arrays (Ni(OH)2@INWA) with rational architectures were prepared. The INWA with small wire diameter and high wire density acts both as miniature conductive scaffold and highly conductive core providing large surface area to load amorphous Ni(OH)2 and ensuring high ionic/electronic conductivities. The amorphous Ni(OH)2 nanosheets in-situ converted from the metallic surface of INWA are in seamless contact with the metallic core forming a close core-shell structure. Because of the material and architecture advantages, the amorphous Ni(OH)2@INWA presents enhanced electrochemical performance of ultrahigh specific capacitances of 3400 F g−1 at a specific current of 5 A g1, remarkable rate capability (3000 F g−1 at 100 A g−1). The asymmetric supercapacitor of Ni(OH)2@INWA//reduced graphene oxide delivers a high specific energy of 53 Wh kg1 at a specific power of 395 W kg−1, and a specific energy of 31 Wh kg−1 can be maintained at a specific power of 4973 W kg−1. It also shows a long-term stability with 91 % retention of the initial capacitance after 10000 cycles at a specific current of 2 A g−1.

Fabrication of self-supported Ni(OH)2@nickel nanowire coreshell arrays with enhanced electrochemical performance for supercapacitor applications

A self-supported nickel nanowire array coated with Ni(OH)2 (Ni(OH)2@SNWA) with enhanced electrochemical performance was successfully fabricated by template-directed electrodeposition and oxidation treatment. Porous polycarbonate membrane was used as the template for the preparation of self-supported nickel nanowire array with a small wire diameter and high wire density. The Ni(OH)2 on the surface formed through oxidation treatment is in close contact with the inside nickel wire. Due to its self-supported and integrated core–shell structure, the Ni(OH)2@SNWA has excellent ionic and electrical conductivities, and shows enhanced electrochemical performance at high current densities.

Micro-drilling characteristics of sequential glass fiber-reinforced resin-based/copper foil multi-layer sheets

High frequency printed circuit board (HFPCB), a sequential glass fiber-reinforced resin-based/copper foil multi-layer sheet, is widely used as printed circuit boards in next-generation 5G communication base stations, radar antenna, smart cars, etc. Micro-holes are key components that enable the interconnections of different layers, fixed electronic components, and high-density wiring. However, hole wall debris and micro-drill breakage during the micro-drilling of sequential glass fiber-reinforced resin-based/copper foil multi-layer sheet negatively affect the quality and reliability of signal transmission. Herein, chip removal, chip morphology, drilling temperature, thrust force characteristics, and hole wall morphology of HFPCB micro-drilling are investigated. The effect of chip morphology on chip removal is analyzed. Additionally, the effects of thrust force and micro-drill breakage are analyzed. The formation mechanism of hole wall debris is proposed. Compared with traditional FR4, the fracture mechanism and control method of micro-drill breakage are proposed by analyzing the characteristics and cause of typical thrust force variations. Results show that the drilling temperature and chip removal of HFPCB are primary factors causing hole wall debris. The morphology of HFPCB chips primarily includes the chips of copper foil, agglomerate chips of resin layer, and mixed copper-foil–resin chips. The increase in prepreg, resin content, and number of multi-layers causes a large amount of cutting heat during HFPCB micro-drilling. Meanwhile, the large thickness, large depth ratio, and diameter resulted in poor chip removal. Subsequently, the constant accumulation of heat in the hole resulted in resin melting, followed by adhering to the hole wall, thus generating hole wall debris through a thermo-mechanical coupling extrusion. The long-term fluctuation of thrust force is the main reason for micro-drill breakage during micro-drilling.

Rationally Designing the Trace of Wire Bonder Head for Large-Span-Ratio Wire Bonding in 3D Stacked Packaging

The increasing miniaturization of functional devices drives the microelectronic industry to pursuit large-span-ratio and high-density wire bonding packaging technology as it can facilely interconnect various chips at a low cost. The design method of wire bonder head trace is urgently needed in the Post Moore Era. Herein, a rational design strategy of wire bonder head trace was proposed. By solving the geometric mapping equations derived from the geometrical evolution of the wire loop, the wire bonder head trace can be easily designed to fit the desired loop profile. The explicit finite element model was also developed to verify the designed wire bonder head trace and disclose the dynamic evolution of strain/stress on wire loops simultaneously. Furthermore, by using orthogonal experimental design, the trace height was found to be the most critical geometric factor influencing loop profiles. The proposed strategy was illustrated to design wire bonder head traces with which large span-ratio loops (>5) with the finest reported gold wire (sub-10 μm) were successfully formed. The mechanical strength tests showed the wire loops were superior to loops with other larger wire. The proposed strategy significantly improves the efficiency of design reliable wire bonder head trace for high-density packaging and will have broad application prospects in microelectronic industry.

Fabrication of Copper Circuit Pattern By Using Solid-Electrodeposition Process

Recently, automotive industry faces to revolution originated from the concept of Connected, Autonomous, Shared and Electric (CASE). For future society, it is noted that electric devices should be increasingly important components because a large number of the devices is indispensable to put CASE in practice. In electric devices, printed circuit boards (PCBs) are particularly key materials, which require further high density wiring as well as cost reduction. The fine patterned PCBs is often fabricated by semi-additive process. However, it is not easy to achieve finer pattering, owing to limitation of photolithographic resolution as well as residual palladium and/or copper metal in etching area. Regarding with the fabrication cost, the drastic reduction cannot be expected without changing process flow because semi-additive process is one of the mature technologies. In addition to that, the exhaust water generated from developing, electroplating, etching and rinsing processes causes serious environmental issues on nature, almost all of which are related to masking and electro/electroless plating processes. Therefore, it is urgently necessary for CASE to develop simple process without masking and conventional plating. We have developed novel electrodeposition process named solid electrodeposition (SED) which is characterized with metal ion electrophoresis through solid electrolyte membrane. The present SED apparatus is shown in Fig. 1. The head part composed of anode electrode, metal solution and the membrane is settled on the tip of press apparatus. The head part contacts with substrate under constant pressure and then a voltage is applied between anode electrode and cathode substrate. The metal deposition proceeds on solid-solid interface between membrane and substrate. It is important to note that cation exchangeable polyelectrolyte is used for membrane, i.e., metal ion can diffuse through ion-exchange reaction. When this system is accumulated into small probe system, this process enables electrodeposition of metals only by attaching the membrane surface into the substrate in a serial patterning manner. Moreover, SED has a merit of relatively high deposition rate, which is characterized with effective mass transfer mechanism of metal ion into membrane. We believe that SED can be highly potential process to dissolve not only the cost but also the environmental issues for current fabrication process of electronic elements. In the current study, we report on the fabrication of PCBs by using SED process. Although SED process can apply for selective deposition, an area of which depends on contact area of membrane used for deposition, it is difficult to match membrane size with fine patterns. Therefore, the patterned seed layer is printed on the substrate before SED process. The deposited copper patterns completely reflect underlying seed patterns without widening metal lines. This is because copper predominantly deposits along height direction, presumably due to selective growth of copper at solid interface. In this contribution, we will report the characteristics of SED process and novel process to fabricate circuit patterns without using masking and rinsing process. Figure 1

The ultra light Drift Chamber of the MEG II experiment

The MEG experiment at the Paul Scherrer Institute searches for the charged Lepton Flavor Violating μ+→e+γ decay. MEG has already determined in a first data taking phase the world best upper limit on the branching ratio: BR(μ+→e+γ)<4.2×10−13 An upgrade of the whole detector has been approved to obtain a substantial increase in sensitivity. Currently MEG is in upgrade phases, this phase involves all the detectors. The new positron tracker is a high transparency single volume, fully stereo cylindrical Drift Chamber (CDCH), immersed in a non uniform longitudinal B-field, with length of 1.93 m, internal radius of 17 cm and external radius of 30 cm. It is composed of 9 concentric layers, divided into 12 identical sector of 16 drift cells. The single drift cell is approximately square, with a 20 μm gold plated W sense wire surrounded by 40 μm silver plated Al field wires in a ratio of 5:1. The total number of wires amounts to 11904 for an equivalent radiation length per track turn of about 1.5x10−3 X0 when the chamber is filled with a gas mixture of helium and iso-butane. Due to the high wire density (12wires∕cm2), the use of the classical feed-through technique as wire anchoring system could hardly be implemented and therefore it was necessary to develop new wiring strategies. The number of wires and the stringent requirements impose the use of an automatic system (wiring robot) to operate the wiring procedures. Several tests have been performed in different prototypes of the drift chamber, exposed to cosmic rays, test beams and radioactive sources, to fulfill the requirement on the spatial resolution to be less than 110 μm. In this paper we describe the CDCH construction and the first tests during the 2018 Engineering Run.

Direct catalyst-free self-assembly of large area of horizontal ferromagnetic ZnO nanowire arrays

Large-area self-assembled horizontal ferromagnetic ZnO nanowire arrays (NWAs) have been successfully prepared by catalyst-free post-annealing treatment on ZnO thin films. XRD, SEM and TEM analysis show that the ZnO nanowires with a hexagonal wurtzite structure are aligned along the 〈112¯0〉 glide directions and the density of wires is an order of magnitude higher than those fabricated using catalyst. Magnetization measurements indicate that the arrays are ferromagnetic at room temperature. It is found that the annealing plays a key role not only in producing nanowire arrays by thermal treatment but also in inducing magnetism by generating vacancies by evaporation. With a high wire density and ferromagnetic ordering, the horizontal NWAs fabricated by the simple annealing method may be useful for fabricating electrical and spintronic devices at nanoscale.

Fabrication of Flexible Superconducting Wiring with High Current-Carrying Capacity Indium Interconnects.

The X-ray integral field unit (X-IFU) is a cryogenic spectrometer for the Advanced Telescope for High ENergy Astrophysics (ATHENA). ATHENA is a planned next-generation space-based X-ray observatory with capabilities that surpass the spectral resolution of prior missions. Proposed device designs contain up to 3840 transition edge sensors, each acting as an individual pixel on the detector, presenting a unique challenge for wiring superconducting leads in the focal plane assembly. In prototypes that require direct wiring, the edges of X-IFU focal plane have hosted aluminum wirebonding pads; however, indium (In) 'bumps' deposited on an interface layer such as molybdenum nitride (MoN) can instead be used as an array of superconducting interconnects. We investigated bumped MoN:In structures with different process cleans and layer thicknesses. Measurements of the resistive transitions showed variation of transition temperature T c as a function of bias and generally differed from the expected bulk T c of In (3.41 K). Observed resistance of the In bump structures at temperatures below the MoN transition (at 8.0 K) also depended on the varied parameters. For our proposed X-IFU geometry (10 μm of In mated to a 1-μm In bump), we measured a minimum T c of 3.14 K at a bias current of 3 mA and a normal resistance of 0.59 mΩ per interconnect. We also investigated the design and fabrication of superconducting niobium (Nb) microstrip atop flexible polyimide. We present a process for integrating In bumps with the flexible Nb leads to enable high-density wiring for the ATHENA X-IFU focal plane.

The Insulating Materials for High Density Wiring Formation on Next Generation’s IC Package

The Insulating Materials for High Density Wiring Formation on Next Generation’s IC Package

The construction technique of the high granularity and high transparency drift chamber of MEG II

The MEG experiment searches for the charged lepton flavor violating decay, μ +→ e+γ. MEG has already determined the world best upper limit on the branching ratio BR<4.2× 10−13 at 90% CL. An upgrade of the whole detector has been approved to obtain a substantial increase in sensitivity. Currently MEG is in upgrade phases, this phase involves all the detectors. The new positron tracker is a single volume, full stereo, small cells drift chamber (DCH) co-axial to the beam line. It is composed of 10 concentric layers and each single drift cell is approximately square 7 mm side, with a 20 μ m gold plated W sense wire surrounded by 40 μ m and 50 μ m silver plated Al field wires in a ratio of 5:1, about 12,000 wires. Due to the high wire density (12 wires/cm2), the use of the classical feed-through technique as wire anchoring system could hardly be implemented and therefore it was necessary to develop new wiring strategies. The number of wires and the stringent requirements on the precision of their position and on the uniformity of the wire mechanical tension impose the use of an automatic system to operate the wiring procedures. This wiring robot, designed and built at the INFN Lecce and University of Salento laboratories, consists of: ⋅ a semiautomatic wiring machine with a high precision on wire mechanical tensioning (better than 0.5 g) and on wire positioning (20 μ m) for simultaneous wiring of multiwire layers;⋅ a contact-less infrared laser soldering tool; ⋅ an automatic handling system for storing and transporting the multi-wire layers. The drift chamber is currently under construction at INFN and should be completed by the end of summer 2017 to be then delivered to PSI for commissioning.