Higher-order Differential Power Analysis Research Articles

Using Genetic Algorithm in Inner Product to Resist Modular Exponentiation From Higher Order DPA Attacks

Evolutionary computation techniques have always provided fascinating results in all the fields of science and engineering. However in the area of computer security, their contribution has been comparatively very less. More specifically if we consider the side-channel attacks, use of these nature based techniques have been very nominal. Therefore, we proposed a secure protocol in this paper to combat against the Higher Order Differential Power Analysis attacks on modular exponentiation based cryptosystems using one of the popular evolutionary computation techniques. The proposed work first uses Genetic Algorithm for splitting the huge exponent within the modular exponentiation into multiple non-uniform shares. Then, this shares are randomly chosen for computing individual modular exponentiation with the help of nearest neighbor algorithm. Using Genetic Algorithm, our proposed protocol can generate reasonable number of shares which exposes secret exponent at the least. As a result, it provides significant resistance to Higher Order Differential Power Analysis attacks. Moreover, randomization in computing individual modular exponentiation secures the cryptosystem from generic power analysis attacks like SPA and DPA.

Resisting HODPA attacks in modular exponentiation using inner product with differential evolution

This paper presents a secured computation of modular exponentiation to resist higher-order differential power analysis (HODPA) attacks in asymmetric cryptosystems like RSA. HODPA attacks can be resisted by segmenting secret sensitive data and its intermediate values into multiple shares. In modular exponentiation-based cryptosystems, the exponent plays a significant part in the secret key. We have used inner product with differential evolution algorithm to segment the exponent into multiple shares. Using entropy-based nearest neighbor algorithm, we have randomly computed independent modular exponentiation to resist SPA and DPA attacks. Analysis was done on 1024, 1536 and 2048 bit RSA. With a pre-computation complexity, the proposed approach can provide significant resistance to SPA, DPA and HODPA attacks against modular exponentiation-based cryptosystems.

New second‐order threshold implementation of AES

In this work, the authors propose some alternative hardware efficient masking schemes dedicated to protect the Advanced Encryption Standard (AES) against higher order differential power analysis (DPA). In general, the existing masking schemes all have in common an intrinsic trade-off between the two main parameters of interest, namely the generation of fresh random masking values and the cost of hardware implementation. The design of efficient masking schemes which are non-expensive in both aspects appears to be a difficult task. In this study, the authors propose a second-order threshold implementation of AES, which is characterised by a beneficial trade-off between the two parameters. More precisely, compared to the masking scheme of De Cnudde et al. at CHES 2016, which currently attains the best practical trade-off, the proposed masking scheme requires 28.4% less random masking bits, whereas the implementation cost is slightly increased for about 13.7% (thus the chip area is 1.4 kGE larger). This masking scheme has been used to implement AES on an field-programmable gate array (FPGA) platform and its resistance against the second-order DPA in a simulated attack environment has been confirmed.

MEAS: memory encryption and authentication secure against side-channel attacks

Memory encryption is used in many devices to protect memory content from attackers with physical access to a device. However, many current memory encryption schemes can be broken using differential power analysis (DPA). In this work, we present Meas—the first Memory Encryption and Authentication Scheme providing security against DPA attacks. The scheme combines ideas from fresh re-keying and authentication trees by storing encryption keys in a tree structure to thwart first-order DPA without the need for DPA-protected cryptographic primitives. Therefore, the design strictly limits the use of every key to encrypt at most two different plaintext values. Meas prevents higher-order DPA without changes to the cipher implementation by using masking of the plaintext values. Meas is applicable to all kinds of memory, e.g., NVM and RAM. For RAM, we give two concrete Meas instances based on the lightweight primitives Ascon, PRINCE, and QARMA. We implement and evaluate both instances on a Zynq XC7Z020 FPGA showing that Meas has memory and performance overhead comparable to existing memory authentication techniques without DPA protection.

A Performance and Area Efficient ASIP for Higher-Order DPA-Resistant AES

Masking is a common method used in embedded systems to prevent differential power analysis (DPA) attack. However, first-order masking cannot prevent higher-order DPA attacks. To enhance security, higher-order masking should be implemented. Hardware accelerator based higher-order masking has higher performance, but it consumes large area. General purpose processor (GPP) based higher-order masking is area-efficient, but it is unable to meet performance requirements. To handle this problem, we propose a novel high-order DPA-resistant ASIP. We develop three performance and area-efficient methods to extend the instruction set for a 32-bit LEON3 processor, with the goal of reducing execution cycles and code sizes. First, we reorder the execution sequence of SubBytes and ShiftRows. We partition new critical pathlthe masked SubBytes followed by the masked MixColumns, and transform computations from $GF(2^8)$ to $GF(2^4)^2$ that efficiently reduces the area. We reused our previous technique, which moved the map and the inverse map functions outside the AES round. Second, we develop an algorithm to search for an optimal transformation matrix of the map function to reduce the critical path of the masked MixColumns. Third, we reuse first-order masked SubBytes for higher-order masked SubBytes to optimize area without compromising performance. The experimental results show that our third-order masking design reduces around 8/9 execution cycles of GPP based reference design and reduces 70.5% area of hardware accelerator based reference design. We have realized a highly secure ASIP with third-order masking that dramatically reduces execution cycles from 197–470 K to only 3.3 K compared with state-of-the-art software implementations.