High Voltage SiC Research Articles

Comparative Performance Evaluation of High-Voltage Bidirectional, Conventional and Superjunction Planar DMOSFETs in 4H-SiC

We quantitively compare the static and dynamic performance for high-voltage SiC bidirectional (BD) conventional and superjunction (SJ) DMOSFETs by using 3D TCAD simulations. We extract the specific on-resistance (RON,sp) and the total specific switching charge (QT,sp), which is a sum of the specific gate charge (QG,sp) and drain charge (QDS,sp) to quantify both the static and switching characteristics respectively. We also develop a new Figure-of-Merit (FoM), which is the product of RON,sp . QT,sp, to evaluate the overall performance. We show that the high-voltage 4H-SiC BD SJ DMOSFET has the best FoM with substantial (>58%) improvement, compared to the BD conventional DMOSFETs, which increases with increasing breakdown voltage.

Updates on Impact Ionisation Triggering of Thyristors

High voltage (HV) generators are used in multiple industrial and scientific facilities. Recent publications have demonstrated that triggering industrial thyristors (relatively slow switching devices) in overvoltage mode, also called impact ionization mode, significantly enhances their dU/dt and dI/dt characteristics. This novel triggering methodology necessitates the application of substantial overvoltage between the thyristor’s anode and cathode, delivered with a swift slew rate exceeding 1 kV/ns. The adoption of compact pulse generators constructed from commercially available off-the-shelf components (COTS) opens up avenues for deploying this technology across various domains, including the implementation of high-speed kicker generators in particle accelerators. In our methodology, we employed commercially available high-voltage SiC MOSFETs along with a custom-designed fast gate driver. This driver was conceptualized based on the recent development of gate boosting techniques, featuring a driving voltage exceeding 600 V. The gate driver for these MOSFETs comprises three key components: a level-shifter with NMOS and PMOS transistors, a compact Marx generator with two avalanche transistors, and a GaN HEMT in a high input and low output impedance configuration. The proposed gate-boosting driver achieves a slew rate exceeding 1 kV/ns for the driving pulse. Furthermore, we demonstrate that with this driver, a 1.7 kV rated SiC MOSFET can produce an output pulse of 1.45 kV and a maximum slew rate of ≈2.5 kV/ns. This gate-boosting driver aims to minimize commutation times, achieves a slew rate of over 1 kV/ns, and handle higher loads, making it ideal for impact ionization triggering of industrial thyristors.

High voltage SiC based calculable impulse voltage calibrator

High voltage SiC based calculable impulse voltage calibrator

Electrical and thermal characterization of (250 °C) SiC power module integrated with LTCC-based isolated gate driver

The high-voltage SiC MOSFET power modules enable high-frequency and high-efficiency power conversion. The parasitic inductances induced by traditional packages of this device technology significantly deteriorate device switching performance, especially in high-temperature applications. In this paper, a novel low-cost discrete SMD component gate driver embedded in a SiC MOSFET power module is introduced. A newly integrated packaging structure has been introduced and proved to be efficient in reducing package-related turn-on loss and turn-off parasitic ringing. However, the gate propagation delay and optocoupler on-chip weak output signal in such a structure become limitations for further pushing the operating frequency and the output current level for high-efficiency power conversion. The electrical characterization of low-temperature co-fired ceramic (LTCC) gate drivers is covered. Furthermore, a 1200 V/120A SiC MOSFET phase-leg power module utilizing high-temperature packaging technologies has been developed. The static characteristics, switching performance, and thermal behavior of the fabricated power module are fully evaluated under operating temperature variations of up to 250 °C.

High Voltage and High Frequency DC Power Supply with Ultra High Voltage SiC Schottky Barrier Diode Modules

High Voltage and High Frequency DC Power Supply with Ultra High Voltage SiC Schottky Barrier Diode Modules

A Reinforcement-Learning Based Approach for Designing High-Voltage SiC MOSFET Guard Rings

A Reinforcement-Learning Based Approach for Designing High-Voltage SiC MOSFET Guard Rings

Fiber-Induced Optical Reflective Cavity in a High-Voltage SiC Photoconductive Switch to Improve Photoelectric Responsivity

Fiber-Induced Optical Reflective Cavity in a High-Voltage SiC Photoconductive Switch to Improve Photoelectric Responsivity

LET and Voltage Dependence of Single-Event Burnout and Single-Event Leakage Current in High-Voltage SiC Power Devices

LET and Voltage Dependence of Single-Event Burnout and Single-Event Leakage Current in High-Voltage SiC Power Devices

Desat Protection With Ultrafast Response for High-Voltage SiC MOSFETs With High dv/dt

Desat Protection With Ultrafast Response for High-Voltage SiC MOSFETs With High <i>dv/dt</i>

A Novel 6500 V SiC Trench MOSFET with Integrated Unipolar Diode for Improved Third Quadrant and Switching Characteristics.

A 6500 V SiC trench MOSFET with integrated unipolar diode (UD-MOS) is proposed to improve reverse conduction characteristics, suppress bipolar degradation, and reduce switching loss. An N type base region under the trench dummy gate provides a low barrier path to suppress hole injection during the reverse conduction operation. The reverse conduction voltage VON is reduced to 1.11 V, and the reverse recovery charge (QRR) is reduced to 1.22 μC/cm2. The gate-to-drain capacitance (CGD) and gate-to-source capacitance (CGS) of the UD-MOS are also reduced to improve switching loss due to the thick oxide layer between the trench gate and dummy gate. The proposed device exhibits an excellent loss-related figure of merit (FOM). It provides a high-voltage SiC MOSFET prototype with potential performance advantages for voltage source converter-based high voltage direct current applications.

Bidirectional Control With Fitting Model-Based Synchronous Rectification and Input Ripple Current Feedforward for SiC Bidirectional CLLC EV Charger

Conventional CLLC Synchronous Rectification (SR) typically adopts detection circuits to sense the high frequency signals. It can hardly be used in the high voltage SiC applications directly as it is sensitive to high dv/dt and may cause false operation. A bidirectional control is proposed for the SiC CLLC charger to achieve the SR function and mitigate the input ripple current. Considering the switching frequency and load, the SR on-time is calculated by the proposed three-order fitting model with low calculation source and high immunity to high dv/dt. Moreover, an input ripple current feedforward control is proposed in the discharging mode, which adds the extracted double line-frequency ripple current to the bus voltage reference. It not only achieves low SR conduction loss, but also reduces the input ripple current largely in the discharge. A 6.6-kW SiC bidirectional CLLC charger was built. Compared to the conventional SR, the CLLC efficiency of proposed SR improves 0.28% at 6.6 kW in the charge. In the discharge, the reduction of CLLC input ripple current at the double line-frequency is up to 91%. The overall charging and discharging efficiencies are 95.4% and 96.1% at full load, respectively.

Piezoelectric Transformer-Based High-Voltage Pulse Generator Using Wide-Bandgap Semiconductors for Medical Electroporation Therapy.

In this paper, a new application of Piezoelectric Transformer (PT)-based power converters to generate high-voltage (HV) bipolar pulses for medical electroporation therapy is proposed. In particular, PT-based power conversion is investigated as an alternative to magnetics-based approaches of generating HV from a relatively low-voltage (LV)input source for application in electroporation therapy. The detailed PT-based system design and selection of wide bandgap semiconductor switches such as GaN FETs, high-voltage SiC diodes and SiC MOSFETs, as well as simulation results to demonstrate proof-of-concept using LTSpice are presented. Preliminary experimental results of the PT-based capacitor charger are shown, and work is ongoing to develop a complete hardware prototype of the proposed HV pulse generator.

Single event burnout failures caused in silicon carbide power devices by alpha particles emitted from radionuclides

Single event burnouts (SEB) threaten the safe operation of high voltage SiC power devices in a wide range of applications. The triggering of this failure mechanism has been widely documented for the case of heavy ions and neutron interactions. In this study, it is demonstrated experimentally that destructive SEB events can be triggered in SiC and Si power devices by single alpha particles in the 5 MeV energy range, such as those emitted by radioactive isotopes. Such SEB events have been observed for blocking voltages lower than the breakdown voltage of the investigated devices. The experimental setup making use of an Am241 planar source to quantitatively observe the current pulses resulting from irradiation is described in detail. The mechanism of SEB initiation by single alpha particles has been investigated by the means of TCAD simulation.The experimental and simulation results show that alpha particles can trigger SEB in both SiC and Si power devices, with SiC devices exhibiting a graver susceptibility. In particular, the simulations demonstrate that the thermal runaway is a consequence of current filamentation in the main blocking junction of the devices, due to generation of a streamer along the ionization track produced by the impinging particle. Furthermore, it is shown that the increased susceptibility of SiC devices to destructive SEB is due to the stronger local field, thinner depleted region and higher junction capacitance than in Si, resulting in higher available energy for the destructive event. The present findings may have practical implications. Given the simplicity and economy of the procedure, alpha sources can be used as a complementary technique to nucleon irradiation for the characterization of the susceptibility of power devices to SEB. Finally, the possible impact on the triggering of SEBs by alpha emitters present as contamination near the active areas of the device should be reconsidered.

Design and Performance of High Voltage Chip-Level Series-Connected SiC MOSFET Module

In medium voltage (MV) and high voltage (HV) applications, HV SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> with a single chip competes with series-connected low voltage (LV) SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> . The cost of the former is high due to immature process, and the parasitic inductance of the latter is large due to series-connected devices. In this article, a novel chip-level series-connected SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> module based on planar packaging is proposed to compromise cost and parasitic inductance. Several LV chips are connected in series through metal layers, and then packaged as a whole. Compared with HV module with a single chip, the proposed module has significant advantages in cost. Considering the effects of the buffer layer and direct bonded copper on the parasitic inductance, junction temperature, thermal stress, and electric field, electro-thermo-mechanical simulation is conducted to optimize the structure. Compared with existing series-connected structures, the parasitic inductance of the proposed module is reduced by at least 50.15%. Finally, 6.5 kV chip-level series-connected module with six 1.2 kV SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> is fabricated and tested. The results show the performance of the proposed module is comparable with that of HV module with a single chip, which means that the application of the proposed module in MV and HV conditions is promising.

Demonstrations of high voltage SiC materials, devices and applications in the solid state transformer

High voltage SiC power devices have been proven as the potential candidates in replacing the Si counterparts to improve the overall power converting efficiency of the power grids and power systems. In this paper, the demonstrations of high voltage materials and devices along with the applications in the power electronic transformer are presented. Through optimizing the temperature and pressure fields, the grown wafer is totally 4H-SiC and no foreign type exists. The FWHM (Full Width at Half Maximum) of the X-ray rocking curve is 23 arcsec, which indicates a high crystalline quality. Moreover, a thick epitaxial layer is then grown on the wafer. The BPD (Basal Plane Dislocation) density of the epitaxial layer is eliminated by converting the BPD to TED (Threading Edge Dislocation) through a proposed doping-induced defect evolution technology. Furthermore, the high voltage SiC MOSFETs with a blocking voltage of over 6.5 kV are fabricated by optimizing the cell and termination structures. The channel region and JFET region are optimized to further improve the device performance. The typical current conducting capability of a single MOSFET is up to 25 A and the breakdown voltage reaches 7.8 kV at a leakage current of 10 μA. The devices are then packaged to form the 6.5 kV/400 A power modules. The current balancing and thermal designs are taken into consideration to improve the reliability of power modules. Finally, the developed SiC modules are applied in a solid state transformer to demonstrate the advantages of SiC devices. The work presented in this article provides an important guide in developing high voltage and high current SiC power devices.

An Impedance-Based Digital Synchronous Rectifier Driving Scheme for Bidirectional High-Voltage SiC LLC Converter

Conventional digital <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LLC</i> synchronous rectifier (SR) control typically uses detection circuits to sense the drain-source voltage of SR MOSFET in low output voltage applications, or gives SR duty cycle only considering the switching frequency in the microcontroller. They are difficult to be applied to the applications of 700-V high voltage and 6.6-kW high power directly due to the high <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dv</i> / <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dt</i> and large SR duty cycle variations, which poses serious challenge for SRs control. A bidirectional impedance-based SR driving scheme is presented for high-voltage SiC <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LLC</i> converter. Based on the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LLC</i> equivalent impedance, mathematical models are built to calculate the SR on-time in the forward and reverse modes, which can be tuned timely when the switching frequency and load vary. Thus, both bidirectional <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LLC</i> performance with high efficiency and high immunity to the switching noise can be achieved without adding auxiliary circuits. A prototype of 300-kHz 6.6-kW SiC bidirectional <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LLC</i> charger was built. Compared to the conventional SR method, the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LLC</i> efficiencies improve 0.3% in the forward and reverse modes at full load by using the proposed SR driving scheme.

Structure dependent piezoelectricity in electrospun PVDF-SiC nanoenergy harvesters

Piezoelectric materials are undeniably one of the most critical advanced materials in the modern era that can be used as energy harvesters and sensors. In many of these applications, flexibility is a key factor in guaranteeing the proper performance and durability of the device. Polyvinylidene fluoride (PVDF) is a structure-dependent piezoelectric polymer that can provide the required flexibility and piezo-response in its electroactive β-phase structure. The present research aims to investigate the effect of SiC additive and process parameters on the β phase formation in electrospun PVDF fibers. For this purpose, PVDF/SiC nanocomposites were prepared by the electrospinning method, and the effects of PVDF solution concentration, SiC wt%, and electrospinning voltage on β-phase fraction were studied using response surface methodology (RSM) approach for experimental design. The uniform and bead-free morphology of the fibers was observed using scanning electron microscopy (SEM). The results showed that the highest β content could be obtained at low PVDF concentrations, high electrospinning voltage and high SiC wt%. The dominant crystalline phase was determined by XRD analysis, and the β-phase fraction in nanocomposites containing different SiC loadings was estimated using FTIR spectroscopy. The presence of SiC nanoparticles enhanced the piezoelectric behavior of PVDF/SiC nanocomposites due to the higher β-phase fraction and improved charge transfer in the vicinity of semiconductive SiC nanoparticles. The optimum sample containing 3.98 wt% SiC nanoparticles was composed of 95.9% β-phase and showed a normalized piezoelectric sensitivity of 0.4737 mV/N, which was improved by about 350% compared to pure PVDF fibers. The obtained results show that PVDF/SiC nanocomposite fibers can be a promising choice for nanoenergy harvesters or flexible sensors with high sensitivity to small external loads. • RSM optimization was performed on the fabrication process of PVDF-SiC fibers. • β fraction was increased with voltage and SiC wt% and decreased with PVDF concentration. • PVDF-SiC nanocomposite fibers generate a significant output voltage upon loading. • 350% increase was observed in piezoelectric sensitivity of optimized PVDF-SiC fibers. • The piezoresponse enhancement was due to higher β fraction and better charge transfer in the vicinity of SiC nanoparticles.

Performance limits of high voltage press-pack SiC IGBT and SiC MOSFET devices

Considering the switching frequency limit and electromagnetic interference, the selection of high voltage SiC IGBT and SiC MOSFET is confusing due to punch-through effect and bipolar characteristics of SiC IGBT. The thermal resistance, static characteristics and dynamic characteristics of SiC IGBT and SiC MOSFET module with Press-Pack packaging are measured to evaluate the switching frequency limit and electromagnetic interfere of them. The tradeoffs of SiC IGBT between switching frequency limit and electromagnetic interfere are less attractive due to the intrinsic characteristics, such as high power loss and punch-through effect. The possible solutions for SiC IGBT are proposed based on the improvement of driving resistor and driving voltage.

Static and Dynamic Performance of Charge-Carrier Lifetime-Tailored High-Voltage SiC p-i-n Diodes With Capacitively Assisted Switching

Static and Dynamic Performance of Charge-Carrier Lifetime-Tailored High-Voltage SiC p-i-n Diodes With Capacitively Assisted Switching

Suppression of stacking fault expansion in a 4H-SiC epitaxial layer by proton irradiation

SiC bipolar degradation, which is caused by stacking fault expansion from basal plane dislocations in a SiC epitaxial layer or near the interface between the epitaxial layer and the substrate, is one of the critical problems inhibiting widespread usage of high-voltage SiC bipolar devices. In the present study, we investigated the stacking fault expansion behavior under UV illumination in a 4H-SiC epitaxial layer subjected to proton irradiation. X-ray topography observations revealed that proton irradiation suppressed stacking fault expansion. Excess carrier lifetime measurements showed that stacking fault expansion was suppressed in 4H-SiC epitaxial layers with proton irradiation at a fluence of 1 × 1011 cm−2 without evident reduction of the excess carrier lifetime. Furthermore, stacking fault expansion was also suppressed even after high-temperature annealing to recover the excess carrier lifetime. These results implied that passivation of dislocation cores by protons hinders recombination-enhanced dislocation glide motion under UV illumination.