High Voltage NMOS Transistors Research Articles

Plasma Charging Damage Affecting Flash Memory Device Encountered at Pad Etch

This paper is to present plasma charging damage affecting 0.18 micron flash memory product. The affected product encountered high voltage N-MOS transistor current leakage. Correlation analysis pointed towards the passivation / pad etch step. Engineering splits were performed to isolate and understand the root cause. Several factors were suspected contributing to the current leakage. These factors are categorized by recipe, consumable kit and product technology (process flow). Further splits were performed with the consumable kits divided into three groups; quartz group, anodized aluminum group and the gas distribution plate group. The focus of this paper is to highlight the combined impact of high power radio frequency (RF) from process recipe with equipment consumable parts intrinsic defect affecting flash memory device causing plasma charging damage. This paper also investigates the effectiveness of electrical test rework procedure utilizing ultraviolet (UV) erase.

Display Driver IC용 Amplifier Input Transistor의 Matching 개선

The voltages for pixel electrodes on LCD panels are supplied with analog voltages from LCD Driver ICs (LDIs). The latest LDI developed for large LCD TV's has suffered from the degradation of analog output characteristics (target voltage: AVO and output voltage deviation: dVO). By the failure analysis, humps in <TEX>$I_D-V_G$</TEX> curves have been observed in high voltage (HV) NMOS devices for input transistors in amplifiers. The hump is investigated to be the main cause of the deviation for the driving current in HV NMOS transistors. It also makes the matching between two input transistors worse and consequently aggravates the analog output characteristics. By simply modifying the active layout of HV NMOS transistors, this hump was removed and the analog characteristics (AVO &dVO) were improved significantly. In the help of the improved analog characteristics, it also became possible to reduce the size of the input transistors less than a half of conventional transistors and significantly improve the integration density of LDIs.

Design and Optimization of a Hot-Carrier Resistant High-Voltage nMOS Transistor

The hot-carrier degradation behavior of a class of high-voltage n-channel drift MOS transistors is experimentally investigated as a function of the geometrical (layout) parameters of the devices. The design restrictions, imposed by reliability requirements, are described as a subset of the space of the geometrical parameters (safe volume) which guarantees a safe hot-carrier operation. The optimization of the specific drain/source on-state resistance of the devices within the safe volume is discussed.