High-voltage Complementary Metal Oxide Semiconductor Research Articles

MightyPix at the LHCb Mighty Tracker — verificationof an HV-CMOS pixel chip's digital readout

MightyPix is a high voltage complementary metal-oxide-semiconductor (HV-CMOS) active pixel sensor, currently being developed for the Mighty Tracker, an upgrade proposed for LHCb in anticipation of the High Luminosity LHC. To ensure that MightyPix will be able to handle the particle hit rates at the Mighty Tracker, which are expected to reach 17 MHz/cm2, simulations of the chip's digital readout mechanism were performed. Using simulated particle hits the chip's performance within the LHCb environment is characterised. For this, a behavioural model of the first prototype, MightyPix1, representing the analogue pixel matrix, together with the synthesised digital logic is used. Simulation results show the MightyPix1 readout mechanism having an efficiency over 99 % up to 20 MHz/cm2. The bottleneck was found to be the speed at which the hits are read out. This yielded new design ideas to improve the readout for MightyPix2, leading to an efficiency of over 99 % up to 30 MHz/cm2.

Neurostimulators for high-resolution artificial retina: ASIC design challenges and solutions

Objective. Neurostimulator is one of the most important part in artificial retina design. In this paper, we discuss the main challenges in the design of application-specific integrated circuit for high-resolution artificial retina and suggest corresponding solutions. Approach. Problems in the design of the neurostimulator for the existing artificial retina have not been solved yet are analyzed and solutions are presented. For verification of the solutions, mathematical proof, MATLAB and Ansys simulations are used. Main results. The drawbacks of resorting to a high-voltage complementary metal oxide semiconductor (CMOS) process to deal with the large voltage compliance demanded by the stimulator output stage are pointed out, and an alternative approach based on a circuit that switches the voltage of the common reference electrode is proposed to overcome. The necessity of an active discharge circuit to remove the residual charge of electrodes caused by an unbalanced stimulus is investigated. We present a circuit analysis showing that the use of a passive discharge circuit is sufficient to suppress problematic direct current in most situations. Finally, possible restrictions on input and output (I/O) count are investigated by estimating the resistive-capacitive delay caused by the interconnection between the I/O pad and the microelectrode array. Significance. The results of this paper clarified the problems currently faced by neurostimulator design for the artificial retina. Through the solutions presented in this study, circuits with more competitiveness in power and area consumption can be designed.

A Point-of-Care Device for Molecular Diagnosis Based on CMOS SPAD Detectors with Integrated Microfluidics.

We describe the integration of techniques and technologies to develop a Point-of-Care for molecular diagnosis PoC-MD, based on a fluorescence lifetime measurement. Our PoC-MD is a low-cost, simple, fast, and easy-to-use general-purpose platform, aimed at carrying out fast diagnostics test through label detection of a variety of biomarkers. It is based on a 1-D array of 10 ultra-sensitive Single-Photon Avalanche Diode (SPAD) detectors made in a 0.18 μm High-Voltage Complementary Metal Oxide Semiconductor (HV-CMOS) technology. A custom microfluidic polydimethylsiloxane cartridge to insert the sample is straightforwardly positioned on top of the SPAD array without any alignment procedure with the SPAD array. Moreover, the proximity between the sample and the gate-operated SPAD sensor makes unnecessary any lens or optical filters to detect the fluorescence for long lifetime fluorescent dyes, such as quantum dots. Additionally, the use of a low-cost laser diode as pulsed excitation source and a Field-Programmable Gate Array (FPGA) to implement the control and processing electronics, makes the device flexible and easy to adapt to the target label molecule by only changing the laser diode. Using this device, reliable and sensitive real-time proof-of-concept fluorescence lifetime measurement of quantum dot QdotTM 605 streptavidin conjugate is demonstrated.

16-Channel biphasic current-mode programmable charge balanced neural stimulation

BackgroundNeural stimulation is an important method used to activate or inhibit action potentials of the neuronal anatomical targets found in the brain, central nerve and peripheral nerve. The neural stimulator system produces biphasic pulses that deliver balanced charge into tissue from single or multichannel electrodes. The timing and amplitude of these biphasic pulses are precisely controlled by the neural stimulator software or imbedded algorithms. Amplitude mismatch between the anodic current and cathodic current of the biphasic pulse will cause permanently damage for the neural tissues. The main goal of our circuit and layout design is to implement a 16-channel biphasic current mode programmable neural stimulator with calibration to minimize the current mismatch caused by inherent complementary metal oxide semiconductor (CMOS) manufacturing processes.MethodsThis paper presents a 16-channel constant current mode neural stimulator chip. Each channel consists of a 7-bit controllable current DAC used as sink and source current driver. To reduce the LSB quantization error and the current mismatch, an automatic calibration circuit and flow diagram is presented in this paper. There are two modes of operation of the stimulator chip—namely, stimulation mode and calibration mode. The chip also includes a digital interface used to control the stimulator parameters and calibration levels specific for each individual channel.ResultsThis stimulator Application Specific Integrated Circuit (ASIC) is designed and fabricated in a 0.18 μm High-Voltage CMOS technology that allows for ±20 V power supply. The full-scale stimulation current was designed to be at 1 mA per channel. The output current was shown to be constant throughout the timing cycles over a wide range of electrode load impedances. The calibration circuit was also designed to reduce the effect of CMOS process variation of the P-channel metal oxide semiconductor (PMOS) and N-channel metal oxide semiconductor (NMOS) devices that will result in charge delivery to have less than 0.13% error.ConclusionsA 16-channel integrated biphasic neural stimulator chip with calibration is presented in this paper. The stimulator circuit design was simulated and the chip layout was completed. The chip layout was verified using design rules check (DRC) and layout versus schematic (LVS) design check using computer aided design (CAD) software. The test results we presented show constant current stimulation with charge balance error within 0.13% least-significant-bit (LSB). This LSB error was consistent throughout a variety stimulation patterns and electrode load impedances.

Tracking and flavour-tagging performance for HV-CMOS sensors in the context of the ATLAS ITK pixel simulation program

The HV-CMOS (High Voltage - Complementary Metal-Oxide Semiconductor) pixel technology has recently risen interest for the upgrade of the pixel detector of the ATLAS experiment towards the High Luminosity phase of the Large Hadron Collider (LHC) . HV-CMOS sensors can be employed in the pixel outer layers (R >15 cm), where the radiation hardness requirements are less stringent, as they could instrument large areas at a relatively low cost. In addition, smaller pixel granularity can be achieved by exploiting sub-pixel encoding technology. Therefore, the largest impact on physics performance, tracking and flavour tagging, could be reached if exploited in the innermost layer (in place of the current IBL) or in the next-to-innermost layer. This proceeding will present studies on tracking and flavour-tagging performance in presence of HV-CMOS sensors in the innermost layer of the ATLAS detector.

High-Voltage Generation in CMOS Photovoltaic Devices by Localized Substrate Removal

This letter reports a localized substrate removal (LSR) process for on-chip electrical isolation to promote the generation of high voltages by backside-illuminated complementary metal–oxide–semiconductor (CMOS) photovoltaic (PV) devices. The proposed four-cell-cascaded CMOS PV module provides an open-circuit voltage of 2.05 V, a short-circuit current of 2.6 mA, and a conversion efficiency of 11% under 40-mW input laser intensity. The proposed LSR approach can also be used for the stacking of additional on-chip PV cells to generate even more voltage without the need for additional processing steps and without compromising device performance. High-voltage CMOS PV modules could be used in voltage-driven microelectronic circuits (>1.8 V) or current-driven light sources (>1 mA) for a variety of applications.

A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics.

This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW.

Speed optimized linear-mode high-voltage CMOS avalanche photodiodes with high responsivity.

Two different speed optimized avalanche photodiodes (APDs) fabricated in a 0.35 μm standard high-voltage (HV) complementary metal-oxide-semiconductor (CMOS) process with a high unamplified responsivity (avalanche gain M=1) of 0.41 A/W at 670 nm are presented. These APDs differ regarding the effective doping of the deep p well (90% and 75%), using lateral well modulation doping. Compared to the -3 dB bandwidth of the unmodulated APD with 100% doping (850 MHz), this optimization leads to an improved bandwidth of 1.02 and 1.25 GHz for the 75% APD and 90% APD, respectively, both at a gain of M=50.

A 9–11-Bit Phase-Interpolating Digital Pulsewidth Modulator With 1000x Frequency Range

A design of a new hybrid-type digital pulsewidth modulator (DPWM) with a wide frequency range of 1000 : 1, from 10 kHz to 10 MHz, is presented. The proposed DPWM has the maximum duty-cycle resolution of 11 bits and consumes the power of 17.5 $\mu\mbox{W}$ at 10 kHz and 2.36 mW at 10 MHz, respectively. The proposed DPWM realizes the upper 5-bit resolution using a programmable digital counter and the lower 6-bit resolution using a current-integrating-type phase interpolator, employing an M2M-ladder current-steering digital-to-analog converter for low power consumption. The operating clock is generated in on-chip using a relaxation oscillator. The prototype integrated circuit fabricated in a 0.25- $\mu\mbox{m}$ high-voltage complementary metal–oxide–semiconductor demonstrates that the proposed DPWM maintains a good linearity across the entire operating range.

Thick detection zone single-photon avalanche diode fabricated in 0.35 μ m complementary metal-oxide semiconductors

An avalanche photodiode (APD) fabricated in 0.35 μm high-voltage complementary metal-oxide semiconductor (CMOS) technology, which was originally optimized for linear mode applications, is characterized in Geiger mode operation. This work shows that the used design concept is also suitable for single-photon detection applications and achieves a photon detection efficiency of 22.1% at 785 nm due to a thick detection zone and 3.5 V excess bias. At this operation point, the single-photon APD achieves good results regarding afterpulsing probability (3.4%) and dark count rate (46 kHz) with respect to the large active diameter of 86 μm.

Blue enhanced vertically stacked quad junction photodetector with opto window

A vertically stacked quad junction photodetector (PD) with an enhanced spectral responsivity for blue light is presented. This PD is implemented in a 0.35 µm high voltage complementary metal-oxide semiconductor (CMOS) technology. In addition, an optical window, an antireflection coating and a modified p + doping are used to attain the enhancement for blue light. The proposed PD is compared against other state of the art implementations and characterised for its spectral response.

Multistable defect characterization in proton irradiated single-photon avalanche diodes

Multistable defect generated by proton irradiation is investigated in single-photon avalanche diodes (SPADs). SPADs under the 11-MeV proton irradiation test, are imple- mented in a 0.35µm high-voltage complementary metal oxide semiconductor technology as an imager array. According to the experimental results, the defect or cluster of defects are located in the space charge region of the SPAD, which modulate the dark response and causes in random telegraph signal noise pattern. The defect charge generation behavior is characterized in different biasing conditions and temperatures.

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

Suppression Techniques of Subthreshold Hump Effect for High-Voltage MOSFET

In this paper, simple but very effective techniques to suppress subthreshold hump effect for high-voltage (HV) complementary metal-oxidesemiconductor (CMOS) technology are presented. Two methods are proposed to suppress subthreshold hump effect using a simple layout modification approach. First, the uniform gate oxide method is based on the concept of an H-shaped gate layout design. Second, the gate work function control method is accomplished by local ion implantation. For our experiments, 0.18 μm 20 V class HV CMOS technology is applied for HV MOSFETs fabrication. From the measurements, both proposed methods are very effective for elimination of the inverse narrow width effect (INWE) as well as the subthreshold hump.

Monolithic H‐bridge brushless DC vibration motor driver with a highly sensitive Hall sensor in 0.18 μm complementary metal‐oxide semiconductor technology

A monolithic low-voltage H-bridge brushless DC (BLDC) vibration motor driver with an integrated high sensitivity Hall sensor has been presented in 0.18 μm high-voltage complementary metal-oxide semiconductor technology. To improve the motor start-up reliability, a full-on start mode is applied to realise a high-speed start sequence by shortening the start-up time. Meanwhile, an active start function is activated to prevent dead point phenomenon if the motor magnet pole sensed by the built-in Hall sensor does not change during the motor starting. This complete one-chip solution for driving the BLDC vibration motors provides significantly enhanced reliabilities, including thermal shutdown and under voltage lockout protection functions, and fully eliminates the need for any external components. The measured results show that the motor driver chip has a typical operating point of 2 mT and a typical releasing point of − 2 mT, showing a hysteresis magnetic property of 4 mT. The chip is very robust. It can operate well within a low supply voltage range of 2–4 V and can output a maximum of 300 mA peak current while the ambient temperature ranges from − 40 to 85°C.

Programmable high voltage CMOS chips for particle-based high-density combinatorial peptide synthesis

We built high voltage complementary metal oxide semiconductor (CMOS) chips that generate electrical fields on their surface, such that electrically charged microparticles (diameter 10–20 μm on average) can be addressed on distinct pixel electrodes according to arbitrary field patterns. Each pixel contains a memory cell in canonical low-voltage CMOS-technology controlling a high voltage (30–100 V) potential area on the top metal layer. Particle transfer with minimal contaminations in less than 10 s for a complete chip was observed for pixels of 100 μm × 100 μm down to 65 μm × 65 μm. This allows a new way to create surface modifications on top of CMOS chips without need for additional masks or stamps. Using suitable particles, a chemically modified chip surface, and compatible chemistry, this method can be utilized for self-aligned high-density biopolymer arrays, e.g., peptide arrays. Transfer of microparticles loaded with amino acids for combinatorial peptide synthesis is demonstrated. Successful synthesis of different peptides (octamers) was proven by immunostaining. Based on results obtained by a chip containing pixel areas of different characteristics, a chip for biological applications with 16,384 pixels (10,000 pixel/cm 2) was built. Good homogeneity of peptide synthesis over the chip area was verified by immunostaining.

P-Channel Lateral Double-Diffused Metal–Oxide–Semiconductor Field-Effect Transistor with Split N-Type Buried Layer for High Breakdown Voltage and Low Specific On-Resistance

Many high voltage complementary metal–oxide–semiconductor (HV-CMOS) processes are modified from a standard 5 V CMOS process by adding an N-type heavily doped layer under the P-well of a HV-PMOS drain terminal to isolate a high voltage P-well from a grounded P-substrate. The limitation of breakdown voltage is dominated by P-well concentration and junction depth. For designing a certain breakdown voltage (BVdss) for a HV-PMOS, the original 5 V CMOS P-well concentration should be decreased, which could degrade 5 V CMOS characteristics, such as NMOS punch through and latch-up immunity. In this study, we demonstrate a novel HV-PMOS based on a split N-type buried layer (NBL), which provides a high BVdss in a HV-CMOS process. The newly proposed device with NBL split under the P-well of a drain electrode increases BVdss without degrading specific on-resistance (Ron,sp) and any added process complexity. From this result, P-well concentration could be increased to improve both 5 V NMOS characteristics and HV-PMOS Ron,sp.

Compact programmable controller for a linear piezo-stepper motor

A design of a compact and low-cost programmable high-voltage pulser for a linear piezo-stepper motor, using an 8 bit reduce instruction set computers (RISC) microcontroller, a high-voltage complementary metal oxide semiconductor (HVCMOS) converter, and an adjustable three-terminal high-voltage regulator is presented. The design consists of 12 independent digital channels of high-voltage output and two-operation modes—normal and smart. The generator is applied as a controller for an approach mechanism in a scanning probe microscope. The motor shows translation of about 1 mm/min with step size of about 100 nm.