High-temperature N2 Annealing Research Articles

Nitrogen Annealing As a Sustainable Method for Interface Trap Passivation in 4H-SiC Mosfets

Silicon Carbide (4H-SiC) has emerged as a leading wide band gap semiconductor for high-power, high-temperature applications1. 4H-SiC metal-oxide semiconductor-field-effect transistors (MOSFETs) have lower power dissipation compared to silicon, allowing for low-noise and high-efficiency all-electric vehicle drives, fast-charging stations, solar inverters, and more. While these devices provide substantial advancements for next-generation energy efficient power systems, 4H-SiC may also offer additional functionality in the form of integrated circuits (ICs) at high temperatures (>300 °C). Because of its high noise immunity and low static power consumption, lateral complementary-metal-oxide-semiconductor (CMOS) IC technology in 4H-SiC is desirable for large-scale integration2. This technology necessitates the use of both n- and p-channel MOSFETs that can operate at high temperatures.Despite the advances of 4H-SiC MOSFETs, the high density of interface states (Dit) at the 4H-SiC/SiO2 interface prevents reaching full potential resulting in high channel resistance and low mobility. Alternatives to nitric oxide (NO) annealing, the most common method adopted to reduce Dit in 4H-SiC3,4, are actively sought due to its toxicity and relatively expensive cost. Annealing in pure nitrogen (N2)5,6 at high temperatures (1400 °C-1600 °C) has been recently demonstrated promising results for 4H-SiC MOSFET processing. In this work, we report Dit measurements consistent with [6] and attempt to correlate the nitrogen areal densities of the near interfacial regions with the Dit for high temperature N2 annealing processes compared to NO. In our study, metal oxide semiconductor capacitors were fabricated on p- and n-type 4H-SiC epitaxial layers. Gate oxides were thermally grown at 1150 °C for 10 h in dry O2 resulting in a ~ 60 nm thick oxide layer. Selected samples are then annealed in flowing N2 at high temperatures (1400 °C, 1 h; 1450 °C, 1 h; and 1500 °C, 30 minutes or 1 h) or NO (1175 °C, 2 h). X-ray photoelectron spectroscopy (XPS), carried out after etching the oxide, indicates that the amount of nitrogen at the interface due to high temperature N2 annealing is ~ 4 × higher than NO annealed devices. Simultaneous high frequency (100 kHz)- low frequency CV was performed to extract interface trap densities (Dit) for each process and compared at room temperature (27 °C) with reference 1175 °C, 2 h NO annealed samples. The comparison reveals that, N2 annealing at 1500 °C for 30 minutes with a flow rate of 3 LPM results in Dit values comparable to NO annealing across the bandgap. Moreover, nitrogen annealing is more effective in reducing Dit near the valence band than NO annealing, while the opposite is true close to the conduction band-edge, consistent with previous reports [6] and observed in atomistic models of these interfaces using the density functional theory7. Nitrogen annealing also decreases the positive fixed charges at the interface of p-type 4H-SiC and SiO2, as evidenced from the flat band voltage comparison. The oxide breakdown voltage for the devices made with 1500 °C N2 annealing was similar to that of NO annealed devices. XPS analysis of the N2 annealed devices, their behavior under high temperature and bias, and their potential to substitute NO will be further discussed.The authors gratefully acknowledge the support from the National Renewable Energy Laboratory/ US Department of Energy sub-contract NREL-AHL-9-92362-01.

Considerations on the kinetic correlation between SiC nitridation and etching at the 4H-SiC(0001)/SiO2 interface in N2 and N2/H2 annealing

The kinetics of the SiC surface nitridation process of high-temperature N2 annealing was investigated with a 4H-SiC(0001)/SiO2 structure based on the correlation between the rates of N incorporation and SiC consumption induced by SiC etching. During the early stage of the annealing process, the rate-limiting step for N incorporation would be the removal of the topmost C atoms in the slow-etching case, while it would be another reaction step, probably the activation process of N, in the fast-etching case. The SiO2 layer thickness and the annealing ambient gas, which serve as the parameters affecting the SiC etching rate, would determine the N incorporation rate according to the kinetic correlation between the N incorporation and SiC etching. The SiC consumption observed during high-temperature annealing in N2 and N2/H2 atmospheres would be induced by active oxidation by residual O2 or H2O in the ambient gas, which would lead to SiC surface roughening.

Improvement of Both n- and p-Channel Mobilities in 4H-SiC MOSFETs by High-Temperature N₂ Annealing

Effects of high-temperature (1400 °C–1600 °C) N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> annealing on the interface states of 4H- SiC/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and the channel mobility of 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) were investigated. It is demonstrated that high-temperature N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> annealing is effective not only for the reduction of the interface state density near the conduction band edge but also for that near the valence band edge. N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> annealing improves channel mobility of both n- and p-channel MOSFETs as in the case of nitric oxide (NO) annealing. In particular, the field-effect mobility of the p-channel MOSFETs annealed in an N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ambient was improved to 17 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs, which is 30% higher than that of NO-annealed MOSFETs. The interface state density estimated from the subthreshold slopes in the MOSFETs is much higher than that extracted by the high–low method but is almost comparable to that estimated by the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\psi _{\text {s}}$ </tex-math></inline-formula> method in both the cases of interface states near the conduction and the valence band edges. These results suggest that there exist fast states (>1 MHz) near the valence band edge, and these fast states affect the channel mobilities of p-channel SiC MOSFETs as in the case of n-channel MOSFETs.

Formation of high-quality SiC(0001)/SiO2 structures by excluding oxidation process with H2 etching before SiO2 deposition and high-temperature N2 annealing

We formed SiC/SiO2 structures by various procedures that excluded an oxidation process. We found that a SiC/SiO2 interface with a low interface state density near the conduction band edge of SiC (D it ∼ 4 × 1010 cm−2 eV−1 at E c −0.2 eV) is obtained for a fabrication process consisting of H2 etching of the SiC surface, SiO2 deposition, and high-temperature N2 annealing. D it is rather high without H2 etching, indicating that etching before SiO2 deposition plays a significant role in reducing D it. The key to obtaining low D it may be the removal of oxidation-induced defects near the SiC surface.

Tailoring the electrical conductivity and hardening in BiFeO3 ceramics

In this report, the influence of cobalt doping and annealing atmosphere on the electrical conductivity and polarization switching of BiFeO3 (BFO) ceramics was studied. Electrical conductivity as well as hardening behavior has been found to increase with introduction of acceptor CoFe' sites. BFO ceramics doped with Co exhibit p-type conductivity, dominated by Fe4+ defects, which can be successfully reduced during high-temperature annealing in N2. However, indications of local reduction were found, presumably on domain walls and grain boundaries. A mechanism of hardening is proposed, which assumes two types of pinning centers: i) VBi''' and FeFe• related and ii) CoFe' and VO•• related, most probably bound into complexes, which are shown to play the key role in the hardening behavior and hysteresis loop pinching and biasing. The results of this study could further promote designing local and bulk conductivity and hardening properties of BFO-based materials.

Sub-nm-Scale Depth Profiling of Nitrogen in NO- and N&lt;sub&gt;2&lt;/sub&gt;-Annealed SiO&lt;sub&gt;2&lt;/sub&gt;/4H-SiC(0001) Structures

We demonstrated an x-ray photoelectron spectroscopy (XPS)-based technique to reveal the detailed nitrogen profile in nitrided SiO2/4H-SiC structures with sub-nanometer-scale-resolution. In this work, nitric oxide (NO)- and pure nitrogen (N2)-annealed SiO2/4H-SiC(0001) structures were characterized. The measured results of NO-annealed samples with various annealing duration indicate that preferential nitridation just at the SiO2/SiC interfaces (~0.3 nm) proceeds in the initial stage of NO annealing and a longer duration leads to the distribution of nitrogen in the bulk SiO2 within few nanometers of the interface. The high-temperature N2 annealing was found to induce not only SiO2/SiC interface nitridation similarly to NO annealing but also SiO2 surface nitridation.

Novel Gate Insulator Process by Nitrogen Annealing for Si-Face SiC MOSFET with High-Mobility and High-Reliability

The gate insulator process for SiC-MOSFET was examined and high-quality interface was realized by employing the pre-annealing process before high-temperature N2 annealing. The pre-annealing evidently activated the interface to introduce nitrogen, and then field-effect mobility exceeded 50 cm2/Vs. The fabricated sample also demonstrated superior bias temperature instability (BTI) and excellent breakdown electric field of 11.7 MV/cm.

Electronic and optical device applications of hollow cathode plasma assisted atomic layer deposition based GaN thin films

Electronic and optoelectronic devices, namely, thin film transistors (TFTs) and metal–semiconductor–metal (MSM) photodetectors, based on GaN films grown by hollow cathode plasma-assisted atomic layer deposition (PA-ALD) are demonstrated. Resistivity of GaN thin films and metal-GaN contact resistance are investigated as a function of annealing temperature. Effect of the plasma gas and postmetallization annealing on the performances of the TFTs as well as the effect of the annealing on the performance of MSM photodetectors are studied. Dark current to voltage and responsivity behavior of MSM devices are investigated as well. TFTs with the N2/H2 PA-ALD based GaN channels are observed to have improved stability and transfer characteristics with respect to NH3 PA-ALD based transistors. Dark current of the MSM photodetectors is suppressed strongly after high-temperature annealing in N2:H2 ambient.

Improvement of Channel Mobility in Inversion-Type n-Channel GaN Metal–Oxide–Semiconductor Field-Effect Transistor by High-Temperature Annealing

Inversion- and depletion-type GaN metal–oxide–semiconductor field-effect transistors (MOSFETs) were fabricated on p- and n--type GaN epitaxial layers, respectively, grown on n+-type on-axis 4H-SiC(0001) substrates. After gate SiO2 was deposited by plasma-enhanced chemical vapor deposition at 350 °C, high-temperature annealing in N2 was carried out to modify the interface. The channel mobility was enhanced with increasing annealing temperature. The device annealed in N2 at 1100 °C after SiO2 deposition showed an inversion channel mobility of 108 cm2·V-1·s-1 at a gate voltage of 15 V. The authors also fabricated MOS capacitors on n--type GaN and characterized the interface state density at the SiO2/GaN interface from capacitance–voltage measurements using the Terman method, of which density was estimated to be in the range of (6–10)×1011 cm-2·eV-1 at an energy level of 0.2 eV below the conduction band edge. The interface state density tended to decrease with increasing annealing temperature, resulting in the improvement of the channel mobility.

High temperature annealing of mnos devices and its effect on si-nitride stress, interface charge density and memory properties

The effects of high temperature annealing in N2 and H2 ambients upon the following properties of MNOS devices have been investigated: Si-nitride stress, etch rate, index of refraction, fixed interface charge and fast surface state density, memory window and charge retention at elevated temperatures. The CVD Si-nitride and Si-oxynitride films were deposited at temperatures as low as 610°C with a NH3/SiH4 ratio of 1000:1, the heat treatments were performed in the temperature range from 640°C to 1130°C. A similar N2-annealing behavior was found for film stress and flatband voltage. The film stress increased with increasing annealing time and temperature while the interface charge density changed from high positive values (QN/q = 4 × 1012cm−2) after nitride deposition at 610°C to high negative values (QN/q = -4 × 1012cm−2) after annealing at 930°C, The fast interface state density increased while the charge retention time was drastically reduced. The changes of the properties by N2 annealing are mainly attributed to decomposition of SiH and NH bonds. Minor effects were obtained by annealing in H2 and the drastic changes caused by N2 annealing could be reversed to a great extent by subsequent H2 annealing. Finally the different effects of deposition and annealing temperature on the propertiesare discussed .