High Speed True Random Number Research Articles

A High-Speed True Random Number Generator Based on Unified Selector-RRAM

A High-Speed True Random Number Generator Based on Unified Selector-RRAM

A high-speed true random number generator based on Ag/SiNx/n-Si memristor

A high-speed true random number generator based on Ag/SiNx/n-Si memristor

Design of Gaussian modulator for continuous-variable quantum key distribution

The continuous-variable quantum key distribution experimental system requires the randomness and speed of a Gaussian modulator. We present the hardware design for a Gaussian random number (GRN) generator based on the Box–Muller method, which can be implemented on a field-programmable gate array (FPGA). An external high-speed true random number generator application-specific integrated circuit (ASIC) is used to this end. The ASIC operates faster and more independently compared with other Gaussian algorithms based on a linear feedback shift register. The trigonometric and logarithmic functions are calculated using the nonuniform piecewise linear approximation. The calculation of the Gaussian random modulus and phase value is realized using this hardware. Compared with an arbitrary waveform generator, the GRN can be uploaded to a computer to estimate the security key rate. Furthermore, the GRN generator accurately provides a Gaussian probability density function that passes the Jarque–Bera inspection and Lilliefors tests. The proposed FPGA-based system is demonstrated to convert eight-channel 320-Mbps uniform random numbers to 40-MHz 16-bit GRN in real time. Finally, the control of the optical module and Gaussian modulation is realized via the FPGA-based outputs of four dual-channel, 16-bit, 1-giga samples per second digital-to-analog converters.

Efficient FPGA implementation of high-speed true random number generator.

High-speed true random number generator is a building block in the modern information security system. We propose and demonstrate an efficient high-speed true random number generator based on multiple parallel self-timed rings (STRs). To improve the security, we evaluate the randomness of the entropy source by min-entropy and exploit the information-theoretically provable Toeplitz-hashing extractor. To minimize the consumption of hardware resources of a field programmable gate array at a predetermined high throughput and maximize the throughput with the limited hardware resources, we systematically derive and investigate the dependence of the data throughput and the total consumed resources of the random number generator on the system parameters. On this basis, we make a joint optimization for the degree of parallelism of the STRs and the extraction efficiency of the extractor. A 10-Gbps true random number generator is implemented efficiently, so that the output random bits can pass all the National Institute of Standards and Technology (NIST) and Dieharder test suites.

A novel ANN-based four-dimensional two-disk hyperchaotic dynamical system, bifurcation analysis, circuit realisation and FPGA-based TRNG implementation

This paper describes the modelling, bifurcation analysis, circuit realisation and FPGA implementation of a novel ANN-based four-dimensional two-disk dynamical system exhibiting hyperchaos and hidden attractor. This paper provides a detailed analysis of the multistability, coexisting attractors and bifurcation properties of the novel two-disk dynamical system with hyperchaos. The novel two-disk dynamical system does not possess any rest point pinpointing the presence of hidden hyperchaotic attractor. We realise the dynamic equations of the two-disk hyperchaotic dynamical system with a real circuit. Next, we build design and implementation of ANN-based two-disk hyperchaotic dynamical system on FPGA. Finally, using FPGA-based implementation of the two-disk hyperchaotic dynamical system, we design and implement a novel high-speed True Random Number Generator (TRNG).

Efficient design of chaos based 4 bit true random number generator on FPGA

True random number generator is a basic building block of any modern secure communication and cryptography system. FPGA implementation of any system has a flexible architecture and low-cost test cycle. In this paper, we present an FPGA implementation of a high speed true random number generator based on chaos oscillator which gives optimize ratio of bit rate to area. The proposed generator is faster and more compact than the existing chaotic oscillator based TRNGs. The Experimental result shows that the proposed TRNG gives 1439 Mbps with optimizing the use of LUTs and registers. It is verified that the generator passes all the NIST SP 800-22 tests. The proposed TRNG is implemented in two FPGA families Nexus 4 (Artix 7) DDR XC7A100TCSG-1 and Basys 3 XC7A35T1CPG236C (Artix 7) using Xilinx Vivado v.2017.3 design suite.

High speed true random number generator with a new structure of coarse-tuning PDL in FPGA * * Project supported by the S&T Plan of Zhejiang Provincial Science and Technology Department (No. 2016C31078), the National Natural Science Foundation of China (Nos. 61574041, 61474068, 61234002), and the K.C. Wong Magna Fund in Ningbo University, China.

A metastability-based TRNG (true random number generator) is presented in this paper, and implemented in FPGA. The metastable state of a D flip-flop is tunable through a two-stage PDL (programmable delay line). With the proposed coarse-tuning PDL structure, the TRNG core does not require extra placement and routing to ensure its entropy. Furthermore, the core needs fewer stages of coarse-tuning PDL at higher operating frequency, and thus saves more resources in FPGA. The designed TRNG achieves 25 Mbps @ 100 MHz throughput after proper post-processing, which is several times higher than other previous TRNGs based on FPGA. Moreover, the robustness of the system is enhanced with the adoption of a feedback system. The quality of the designed TRNG is verified by NIST (National Institute of Standards and Technology) and also accepted by class P1 of the AIS-20/31 test suite.

High-speed true random number generation based on paired memristors for security electronics

True random number generator (TRNG) is a critical component in hardware security that is increasingly important in the era of mobile computing and internet of things. Here we demonstrate a TRNG using intrinsic variation of memristors as a natural source of entropy that is otherwise undesirable in most applications. The random bits were produced by cyclically switching a pair of tantalum oxide based memristors and comparing their resistance values in the off state, taking advantage of the more pronounced resistance variation compared with that in the on state. Using an alternating read scheme in the designed TRNG circuit, the unbiasedness of the random numbers was significantly improved, and the bitstream passed standard randomness tests. The Pt/TaOx/Ta memristors fabricated in this work have fast programming/erasing speeds of ∼30 ns, suggesting a high random number throughput. The approach proposed here thus holds great promise for physically-implemented random number generation.

Design and validation of high speed true random number generators based on prime-length ring oscillators

This paper presents a wide supply voltage range, high speed true random number generator (TRNG) based on ring oscillators, which have different prime number of inverters. And a simple Von Neumann corrector as post processing is also realized to improve data randomness. Prototypes have been implemented and fabricated in 0.18 µm complementary metal oxide semiconductor (CMOS) technology with a wide range of supply voltage from 1.8 V to 3.6 V. The circuit occupies 4 500 µm2, and dissipates minimum 160 µW of power with sampling frequency of 20 MHz. Output bit rate range is from 100 kbit/s to 20 Mbit/s. Statistical test results, which were achieved from the dieHard battery of tests, demonstrate that output random numbers have a well characteristic of randomness.

Design of a high-repetition rate photon source in a quantum key distribution system

Photon source with high-repetition quantum message transmission is needed in the quantum key distribution (QKD) system for long distance and high-repetition rate. We design high-repetition-rate weak coherent light by applying a practical QKD system with decoy states and polarization coding including an FPGA-based true random number generator, narrow pulse shaping under the modulation of high-speed true random number as well as its laser driver. The test indicates that the repetition rate of such light can attain a high performance of 650 MHz, pulse width less than 300 ps, stability of pulse amplitude better than 5%, and extinction rate better than 1000:1.

High speed true random number generator based on open loop structures in FPGAs

Most hardware “True” Random Number Generators (trng) take advantage of the thermal agitation around a flip-flop metastable state. In Field Programmable Gate Arrays (fpga), the classical trng structure uses at least two oscillators, build either from pll or ring oscillators. This creates good trng albeit limited in frequency by the interference rate which cannot exceed a few Mbit/s. This article presents an architecture allowing higher bit rates while maintaining provable unconditional security. This speed requirement becomes stringent for secure communication applications such as the cryptographic quantum key distribution protocols. The proposed architecture is very simple and generic as it is based on an open loop structure with no specific component such as pll.