High Speed Transceiver Logic Research Articles

Core i7 Specific Energy Efficient Ram Design for IoT Application

Fundamental memory has turned out to be one of largest contributors to overall energy consumption and offer many opportunities for power reduction. Power dissipation plays important role in portable products that can store, receive and transmit data because in each operation cycle the power is consumed by the operator. The goal of this paper is to use Frequency scaling approach in Random Access Memory to minimize power dissipation by the help of High Speed Transceiver Logic (HSTL) input output standard. These techniques cover RTL coding. This research suggest that there is 75% reduction clock power 66.66% reduction in Signal power, (35.20% to 47.77%) reduction in IOs power when the frequency are minimize. This design is implemented on Artex-7.

Different I/O Standard and Technology Based Thermal Aware Energy Efficient Vedic Multiplier Design for Green Wireless Communication on FPGA

This paper deals with low power multiplier design that plays a significant role in green wireless communications systems. Over the period of time, researchers have proposed various multiplier designs in order to get high speed. Vedic multiplier is considered as one of the low power multiplier along with high speed as compared with traditional array and booth multipliers. Vedic Multiplier contains a total of sixteen algorithms/sutras for predominantly logical operations. This research focuses on thermal aspects and energy efficiency of wireless communications systems with the thermal aware low power design of Vedic Multiplier. Temperature plays an important role on the performance of any device. The primary purpose of this research is to enhance the thermal stability of the wireless communications. Energy efficient IO standards are used to decrease the power dissipation of Vedic Multiplier and that eventually decrease power dissipation of wireless communications systems. In order to study the effect of different process technology (40, 65, 90 nm) on our design, a novel design is implemented on 40, 65 and 90 nm based FPGA. In this work, we are integrating thermal aware design approach for energy efficient Vedic Multiplier on various FPGA using LVCMOS and HSTL I/O standard. LVCMOS is an acronym for Low Voltage Complementary Metal Oxide Semiconductor and HSTL is an acronym for High Speed Transceiver Logic. In this Vedic Multiplier, we are using three LVCMOS I/O standard and nine HSTL I/O standard. In order to test the thermal sustainability of our Vedic Multiplier design, we are testing it in three different room temperatures i.e. 20, 30, and 40 °C. Using LVCMOS25, there is 12.99, 19.23 and 10.28% reduction in power dissipation on 90, 65 and 40 nm FPGAs respectively. For LVCMOS25, when our Vedic Multiplier design is migrated from 40 nm design to 90 nm FPGA design, there is 87.72% reduction in power dissipation of Vedic Multiplier when temperature is kept constant at 20 °C. When temperature is scaled down from 50 to 20 °C there is 12.45, 14.93, 12.84, 9.45 and 8.48% saving in power dissipation on using HSTL_I, HSTL_I_12, HSTL_I_18, HSTL_I_DCI and HSTL_I_DCI_18 IO Standard respectively on 90 nm FPGA.

HSTL IO Standards Based Processor Specific Green Counter Design on 90nm FPGAAbhay Saxena

Extending battery life and increase in portability of modern electronic devices and gadgets are the main motives behind the Green Computing which is also known by similar terms like energy efficient design or low power design or green design. Such efficiency is only possible if all the components of processor are also energy efficient. In this work, the researchers tried to analyze the energy optimization possibility in counter design by selection of energy efficient IO standards. The researchers had used High Speed Transceiver Logic for the purpose of energy efficient counter design on Spartan3 (90nm) FPGA (field-programmable gate array) using VHDL (VHSIC Hardware Description Language) hardware description language along with the Xilinx ISE simulator for the analysis and synthesis of counters. Spartan 3 with 90 nm low power is used to achieve substantial power savings. Here, researchers have used five different HSTL IO standards for this work. The standards used are HSTL_I, HSTL_III, HSTL_III_18, HSTL_III_DCI and HSTL_II_18. With these sets of IO standards, Researchers had run their counter design on various device operating frequencies (1.0 GHz to 4.0 GHz). The results clearly indicate that this dynamic frequency (1.0 GHz in lieu of 4.0 GHz) scaling had saved 45% of total power.

Design and Performance Analysis of RAM_WR_ Control Module using Xilinx ISE 14.2

In the following work RAM_Write_Control module has been designed and its performance has been analyzed in terms of utilization of power and energy in order to make it energy and power efficient. The main idea behind this unit is to control the data write operation to the core which is used for saving the raw data in impedance measurement module of Electrical Impedance Tomography (EIT) system, KHU Mark 2.5. The performance of the unit is analyzed using 14.2 version of Xilinx software at Virtex-5 FPGA chip. The total power consumption of 3 logic families HSTL (High Speed Transceiver Logic), LVCMOS (Low Voltage Metal Oxide Semiconductor) and LVTTL (Low Voltage Transistor-Transistor Logic) at different I/O Standards have been compared in order to excrete out the most energy efficient logic family. Frequency scaling technique has also been applied by varying the frequencies at a scale of 100 Hz i.e., from 400MHz to 500 MHz to 600 MHz to 700 MHz in a way to find out the most power efficient frequency. It has been observed minimum power consumption occurs in case if we use LVCOMS15 I/O standard of LVCMOS logic family in comparison to other IO standards of other 2 logic families. And this maximum power savage occurs at a lowest frequency of 400 MHz.

HSTL IO Standard Based Energy Efficient Multiplier Design using Nikhilam Navatashcaramam Dashatah on 28nm FPGA

In this paper we have designed an energy efficient multiplier using Nikhilam Navatashcaramam Dashatah Vedic technique. Vedic mathematics consists of 16 sutras and these sutras were used by our ancient scholars for doing there calculation faster, when there were no computers and calculators. Nikhilam Navatasaman is a Sanskrit word which menas “all from 9 and the last from 10”. In today’s work the demand is high speed, efficiency and should take lesser time. Appling these Vedic techniques reduces the system complexity, execution time, area, power and is stable and hence is efficient method. In this paper we have designed an energy efficient multiplier that consists of three inputs and one output. The temperature has been kept constant that is 25 degree Celsius. Airflow has been kept 250 LFM and medium Heat sink. IO Standards has been varied in order to achieve an energy efficient device. In this paper we have taken HSTL (High Speed Transceiver Logic) IOSTANDARD. In order to achieve speed and high performance in addition to energy efficiency, HSTL IO standard is used. HSTL family consists of HSTL _I, HSTL_II, HSTL_I_18 and HSTL_II_18, HSTL_I_12 and the analysis has been done on these IO standards. Frequency scaling is one of the best energy efficient techniques for FPGA based VLSI design and is used in this paper. At the end we can conclude that we can conclude that there is 23-40% saving of total power dissipation by using SSTL IO standard at 25 degree Celsius. The main reason for power consumption is leakage power at different IO Standards and at different frequencies. In this research work only FPGA work has been performed not ultra scale FPGA.

28nm FPGA based Power Optimized UART Design using HSTL I/O Standards

UART abbreviated as Universal Asynchronous Receiver Transmitter is one of the essential element of communication system. It is being mostly used when there is a short-distance, between computer and peripherals. Whenever there is low-cost data exchange or the speed required for transmission is not high, UART’s are also being used there. For the achievement of compact, stable and reliable data transmission, the implementation of UART with VHDL language can be integrated into FPGA. The Total power and Junction temperature of UART have been analyzed in the following paper when it is operating on different I/O standards of HSTL (HIGH SPEED TRANSCEIVER LOGIC) logic family and different range of frequencies from 1 GHz to 46 GHz. Analysis have also been done for two different 28nm FPGA’s which helps to compare the total power reduction at two different FPGA technology so that the best suited FPGA for UART design consuming the least could be discovered. After analysis, it has been concluded that 91.96% of the total power can be saved in the case Kintex-7 and 91.98% of total power can be preserved in case of Artix-7 by operating the design at a frequency of 1 GHz. On the other hand the Junction temperature has been reduced to 11.84% in case of Kintex-7 and it has been reduced to 15.28% in case of Artix-7.

Temperature Control of Pseudo Noise Generator Based Optical Transmitter using Airflow and Heat Sink Profile at High Speed Transceiver Logic IO Standard

Junction temperature is the final temperature of any device, after that device became dead. In this paper, junction temperature of target device i.e. Pseudo Noise sequence random generator based optical transmitter is controlled using heat sink profile and airflow. Heat sink and airflow are the cooling techniques for thermal efficient design on FPGA. We operated target device at high speed transceiver logic (HSTL) on FPGA at 1, 10,100 and 1000 (GHz) operating frequency. Each IO standard is examined with two airflow values (250 MFL and 500MFL) and Heat sink values (Low profile, Medium profile and high profile). For HSTL_I the reduction in junction temperature is (4%, 5%, 16% and 20%), HSTL_III (2%, 4%, 40%, and 67%), HSTL_I_18 (2%, 15%, 59%, and 68%), HSTL_III_18 (2.4%, 19%, 62%, and 74%) is recorded at respective frequencies. Significant reduction of 74% in junction temperature is observed at 1000GHz using HSTL_III_18. We conclude that for frequencies above 10GHz the heat sink profile and air flow significantly reduces the junction temperature using HSTL_III_18. This design makes the target device, energy efficient, system will be integrated with other optical components to make optical communication system green. Xilinx ISE14.7.1.2 design tool is used to perform the experiment.

HSTL을 이용한 전송선로에서의 데이터 전송특성 시뮬레이션

Tosin backplane system design of this study (Backplane) from the HSTL (High-Speed Transceiver Logic) characteristics of the transmit and receive data using the HSPICE simulations and the actual implementation on the FPGA Data transmission characteristics were described by comparing the simulation results. Simulation and measurement criteria for point to point data transmission characteristics of wire length possible to send and receive data about the speed limits were reviewed. Measured point to point connection to send and receive signals at terminal velocity, the factors that affect the electrical noise around the wire length and showed a very important role.