High-speed SiGe Heterojunction Bipolar Transistors Research Articles

THz Direct Detector and Heterodyne Receiver Arrays in Silicon Nanoscale Technologies

The main scope of this paper is to address various implementation aspects of THz detector arrays in the nanoscale silicon technologies operating at room temperatures. This includes the operation of single detectors, detectors operated in parallel (arrays), and arrays of detectors operated in a video-camera mode with an internal reset to support continuous-wave illumination without the need to synchronize the source with the camera (no lock-in receiver required). A systematic overview of the main advantages and limitations in using silicon technologies for THz applications is given. The on-chip antenna design challenges and co-design aspects with the active circuitry are thoroughly analyzed for broadband detector/receiver operation. A summary of the state-of-the-art arrays of broadband THz direct detectors based on two different operation principles is presented. The first is based on the non-quasistatic resistive mixing process in a MOSFET channel, whereas the other relies on the THz signal rectification by nonlinearity of the base-emitter junction in a high-speed SiGe heterojunction bipolar transistor (HBT). For the MOSFET detector arrays implemented in a 65 nm bulk CMOS technology, a state-of-the-art optical noise equivalent power (NEP) of 14 pW/ $\sqrt {Hz}$ at 720 GHz was measured, whereas for the HBT detector arrays in a 0.25 μm SiGe process technology, an optical NEP of 47 pW/ $\sqrt {Hz}$ at 700 GHz was found. Based on the implemented 1k-pixel CMOS camera with an average power consumption of 2.5 μW/pixel, various design aspects specific to video-mode operation are outlined and co-integration issues with the readout circuitry are analyzed. Furthermore, a single-chip 2 × 2 array of heterodyne receivers for multi-color active imaging in a 160–1000 GHz band is presented with a well-balanced NEP across the operation bandwidth ranging from 0.1 to 0.24 fW/Hz (44.1–47.8 dB single-sideband NF) and an instantaneous IF bandwidth of 10 GHz. In its present implementation, the receiver RF bandwidth is not continuously covered but divided into six bands centered around 165, 330, 495, 660, 820, and 990 GHz.

Carry Chains for Ultra High-Speed SiGe HBT Adders

Adder structures utilizing SiGe Hetero-junction Bipolar Transistor (HBT) digital circuits are examined for use in high clock rate digital applications requiring high-speed integer arithmetic. A 4-gate deep test structure for 32-bit addition using a 210 GHz fT process has been experimentally verified to operate with 37.5 ps delay or 26.7 GHz speed. The paper documents a unique blend of CML and ECL circuit innovations, which is needed to obtain this result. The chip is estimated to have a power-delay product of 109 ps-W at a device temperature of 85°C . A low power design is shown to have a power-delay product of 48 ps-W at 21.7 GHz. Speed-power trade-offs are explored through pure ECL logic and varying current. Additionally, with next generation SiGe HBTs, this work shows that 40 GHz is achievable at slightly above room temperature.

Analytical modelling of 200 GHz SiGe HBT high-frequency noise parameters

This paper presents an analytical model for high-frequency noise of high-speed SiGe heterojunction bipolar transistors (HBTs). The model allows circuit level noise parameters to be obtained: the minimum noise figure, the noise resistance and the optimum admittance for different bias and frequencies up to 64 GHz, including the quasi-saturation effect. The noise parameters are determined directly from y-parameters. The analytical model is verified through comparison with TCAD simulation results of the noise parameters using the field impedance method as well as with measured data. The paper also reviews for 200 GHz SiGe HBTs the latest y-parameters-based analytical noise models. Their bias and frequency dependence is calculated and compared with device simulation.

A MEM-varactor tuned, 7.8 GHz differential LC voltage-controlled oscillator

In this paper, design and realization of a parallel plate dual gap MEM-varactor tuned −G m LC voltage controlled oscillator (VCO) is presented. The VCO is implemented with AMS 0.35 μm-SiGe BiCMOS process that includes high-speed SiGe Heterojunction Bipolar Transistors (HBTs). MEM-varactor is fabricated by in-house capabilities and includes six layers and five mask steps. MEM-varactor and VCO is integrated on a FR4 substrate using wire bonder. With the actuation voltage of 0–10 V, 80 MHz tuning range is measured from MEM-varactor integrated VCO that is in the range 7.72 GHz to 7.80 GHz. Fundamental frequency output power changes between −2 dBm and 0 dBm, without the losses depending on the tuning voltage. VCO achieved phase noise of −73.9 dBc/1 Hz.

Design of a 4.2–5.4 GHz differential LC VCO using 0.35 μm SiGe BiCMOS technology for IEEE 802.11a applications

In this paper, a 4.2–5.4 GHz, −Gm LC voltage controlled oscillator (VCO) for IEEE 802.11a standard is presented. The circuit is designed with AMS 0.35 μm SiGe BiCMOS process that includes high-speed SiGe Heterojunction Bipolar Transistors (HBTs). According to post-layout simulation results, phase noise is −110.7 dBc/Hz at 1 MHz offset from 5.4 GHz carrier frequency and −113.4 dBc/Hz from 4.2 GHz carrier frequency. A linear, 1200 MHz tuning range is obtained from the simulations, utilizing accumulation-mode varactors. Phase noise was also found to be relatively low because of taking advantage of differential tuning concept. Output power of the fundamental frequency changes between 4.8 dBm and 5.5 dBm depending on the tuning voltage. Based on the simulation results, the circuit draws 2 mA without buffers and 14.5 mA from 2.5 V supply including buffer circuits leading to a total power dissipation of 36.25 mW. The circuit layout occupies an area of 0.6 mm2 on Si substrate, including DC and RF pads. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2007.

Structure Optimization of Trench-Isolated SiGe HBTs for Simultaneous Improvements in Thermal and Electrical Performances

The current level in the modern high-speed SiGe heterojunction bipolar transistors (HBTs) continues to increase for operation speed enhancement, but the resultant self-heating and elevated junction temperature emerge as a growing concern for device reliability as well as performance. To address such thermal issues, the optimization of SiGe HBT structures to achieve simultaneous improvements in thermal and electrical performance is carried out in this study. As a foundation for the study, an R/sub th/ measurement method and a geometry-based fast analytic thermal model were first developed for trench-isolated SiGe HBTs. Based on the method and model, a set of device design points for lowered R/sub th/ without compromising the RF performance have been successfully proposed and experimentally verified on IBM's 200-GHz SiGe HBTs. The details of the proposed structures and acquired results will be described in detail in the paper. The results obtained in this study shed a light on the possibility of the simultaneous optimization of thermal and electrical performance of SiGe HBTs.

Speed optimized diode-triggered SCR (DTSCR) for RF ESD protection of ultra-sensitive IC nodes in advanced technologies

A novel diode-triggered silicon-controlled rectifier (DTSCR) (Mergens et al., 2003) electrostatic discharge (ESD) protection element is introduced for low-voltage application (signal and supply voltages /spl les/ 1.8 V) with extremely narrow ESD design margins. Trigger-voltage engineering in conjunction with fast and efficient SCR voltage clamping is applied for the protection of ultrasensitive circuit nodes, such as SiGe heterojunction bipolar transistor (HBT) base regions (e.g., f/sub Tmax/=45 GHz in BiCMOS 0.35-/spl mu/m LNA input) and thin gate oxides (e.g., t/sub ox/=1.7 nm in CMOS 0.09-/spl mu/m high-speed input). Ultrathin gate protection requires a reinforced trigger diode chain to avoid SCR trigger-speed issues resulting in critical trigger-voltage overshoots for very fast ESD transients such as a charged device model (CDM). SCR integration can be realized based on parasitic n-p-n/p-n-p inherent to CMOS devices or can alternatively be implemented based on vertical high-speed SiGe HBT with adjacent p+ SCR anode.

MULTI-GHzSiGe BiCMOS FPGAs WITH NEW ARCHITECTURE AND NOVEL POWER MANAGEMENT TECHNIQUES

The availability of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices has opened a door for GHz Field Programmable Gate Arrays (FPGAs).1,2 The integration of high-speed SiGe HBTs and low-power CMOS gives a significant speed advantage to SiGe FPGAs over CMOS FPGAs. In the past, high static power consumption discouraged the pursuit of bipolar FPGAs from being scaled up significantly. This paper details new ideas to reduce power in designing high-speed SiGe BiCMOS FPGAs. The paper explains new methods to reduce circuitry and utilize a novel power management scheme to achieve a flexible trade-off between power consumption and circuit speed. In addition, new decoding logic is developed with shared address and data lines. A SiGe FPGA test chip based on the Xilinx 6200 architecture has been fabricated for demonstration.

Substrate current based avalanche multiplication measurement in 120 GHz SiGe HBTs

A new substrate current-based technique for measuring the avalanche multiplication factor (M - 1) in high-speed SiGe heterojunction bipolar transistors (HBTs) is proposed. The technique enables M - 1 measurement at high operating current densities required for high-speed operation, where conventional techniques fail because of self-heating. Using the proposed technique, M - 1 was measured up to 10 mA/μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> on SiGe HBTs featuring 120 GHz peak f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> which occurs at J/sub C/ about 7 mA/μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Implications for circuit applications are also discussed.

High-speed SiGe HBTs and their applications

The structure of a high-speed self-aligned SiGe heterojunction bipolar transistor (HBT) was optimized through investigations of its characteristics related to the collector-base and emitter-base junctions. The SiGe HBT was fabricated by selective-epitaxial growth (SEG). As a result of the optimization, its cutoff frequency was increased to 130 GHz and its ECL gate-delay time was reduced to 5.3 ps. Based on this SiGe HBT, an IC chipset for 40 Gb/s optical-fiber-links, a 5.8 GHz electronic-toll-collection transceiver IC, and high-speed frequency divider ICs (operating up to the millimeter-wave band) were developed.

Product applications and technology directions with SiGe BiCMOS

In this paper, we highlight the effectiveness and flexibility of SiGe BiCMOS as a technology platform over a wide range of performance and applications. The bandgap-engineered SiGe heterojunction bipolar transistors (HBTs) continue to be the workhorse of the technology, while the CMOS offering is fully foundry compatible for maximizing IP sharing. Process customization is done to provide high-quality passives, which greatly enables fully integrated single-chip solutions. Product examples include 40-Gb/s (OC768) components using high-speed SiGe HBTs, power amplifiers compatible for cellular applications, integrated voltage-controlled oscillators, and very high-level mixed-signal integration. It is argued that such key enablements along with the lower cost and higher yields attainable by SiGe BiCMOS technologies will provide competitive solutions for the communication marketplace.

Reliability of high-speed SiGe heterojunction bipolar transistors under very high forward current density

As device scaling for higher performance bipolar transistors continues, the operation current density increases as well. To investigate the reliability impact of the increased operation current density on Si-based bipolar transistors, an accelerated-current wafer-level stress was conducted on 120-GHz SiGe heterojunction bipolar transistors (HBTs), with stress current density up to as high as J/sub C/=34 mA//spl mu/m/sup 2/. With a novel projection technique based on accelerated-current stress, a current gain shift of less than /spl sim/15% after 10/sup 6/ h of operation is predicted at T=140/spl deg/C. Degradation mechanisms for the observed dc parameter shifts are discussed for various V/sub BE/ regions, and the separation of the current stress effect from the self-heating effect is made based on thermal resistance of the devices. Module-level stress results are shown to be consistent with wafer-level stress results. The results obtained in this work indicate that the high-speed SiGe HBTs employed for the stress are highly reliable for long-term operation at high operation current density.

A comparison of SEU tolerance in high-speed SiGe HBT digital logic designed with multiple circuit architectures

The single-event upset (SEU) responses of three D flip-flop circuits, including two unhardened, and one current-sharing hardened (CSH) circuit, are examined using device and circuit simulation. The circuit that implements the conventional D flip-flop logic using standard bipolar NAND gates shows much better SEU performance than the other two. Cross coupling at transistor level in the storage cell of the other two circuits increases their vulnerability to SEU. The observed differences are explained by analyzing the differential output of the emitter coupled pair being hit. These results suggest a potential path for achieving sufficient SEU tolerance in high-speed SiGe heterojunction bipolar transistor (HBT) digital logic for many space applications.

40-Gb/s circuits built from a 120-GHz f/sub T/ SiGe technology

Product designs for 40-Gb/s applications fabricated from SiGe BiCMOS technologies are now becoming available. In this paper we first briefly discuss heterojunction bipolar transistor (HBT) device operation at high speed, demonstrating that perceived concerns regarding lower BV/sub CEO/ and higher current densities required to operate silicon HBTs at such high speeds do not in actuality limit design or performance. The high-speed portions of the 40-Gb/s system are then addressed individually. We demonstrate the digital capability through a 4: 1 multiplexer and a 1 : 4 demultiplexer running over 50 Gb/s error free at a -3.3-V power supply. We also demonstrate a range of analog elements, including a lumped limiting amplifier which operates with a 35-GHz bandwidth, a transimpedance amplifier with 220-/spl Omega/ gain and 49.1-GHz bandwidth, a 21.5-GHz voltage-controlled oscillator with over -100-dBc/Hz phase noise at 1-MHz offset, and a modulator driver which runs a voltage swing twice the BV/sub CEO/ of the high-speed SiGe HBT. These parts demonstrate substantial results toward product offerings, on each of the critical high-speed elements of the 40-Gb/s system.

Mixed mode circuit and device simulation of RF harmonic distortion for high-speed SiGe HBTs

Mixed mode circuit and device simulation has been used to investigate the linearity properties––harmonic distortion of high-speed low voltage SiGe heterojunction bipolar transistors (HBTs). The simulation test-circuit included the active device, modeled by finite element simulation, as well as passive elements in a SPICE circuit for DC-feed and AC-coupling of the RF-signal. Different Ge-profiles for reduced harmonic distortion have been investigated and compared to a conventional high-speed graded Ge-profile. To find an optimized Ge-profile for RF-applications other figure-of-merits, such as maximum cut-off frequency and minimum noise figure were also simulated. Using the same mixed mode simulation approach the design of the epitaxial collector doping profile for high breakdown voltage, high cut-off frequency and reduced harmonic distortion was investigated.

A Base-Collector Architecture for SiGe HBTs using Low-Temperature CVD Epitaxy Combined with Chemical-Mechanical Polishing

A new collector technology intended for an integrated high-speed SiGe heterojunction bipolar transistor (HBT) is reported. The collector was fabricated by selective epitaxial growth (SEG) using chemical vapor deposition at 770°C under reduced pressure (20 torr) using SiH2Cl2 as silicon precursor and PH3 as n-type dopant source. Chemical-mechanical polishing (CMP) was applied to the overgrown SEG collector in order to achieve a smooth surface in level with the surrounding oxide. Finally, a SiGe base doped with boron was deposited using non-selective epitaxial growth (NSEG) at 650°C. The topography of the collector is inspected after each process step by atomic force microscopy and the topography of the completed collector/base stack indicates that this structure is promising for fabrication of the emitter window. A further advantage with the CMP procedure is the elimination of phosphorous segregation as evidenced by secondary ion mass spectroscopy of the base-collector stack.