High-speed Serial Interconnect Research Articles

A 65 nm 2-Billion Transistor Quad-Core Itanium Processor

This paper describes an Itanium processor implemented in 65 nm process with 8 layers of Cu interconnect. The 21.5 mm by 32.5 mm die has 2.05B transistors. The processor has four dual-threaded cores, 30 MB of cache, and a system interface that operates at 2.4 GHz at 105degC . High speed serial interconnects allow for peak processor-to-processor bandwidth of 96 GB/s and peak memory bandwidth of 34 GB/s.

A new distributed management mechanism for ASI based networks

Advanced Switching Interconnect (ASI) is a high-speed serial interconnect embodied in the Dolphin Express family of interconnect products. In order to support high availability, the ASI specification established a management infrastructure, which is in charge of maintaining network operation after the occurrence of a topological change. When such a change occurs, the management mechanism discovers the new topology, calculates a set of valid routing paths, and distributes them to endpoints within the fabric. Several implementations for such a management mechanism have been proposed that use a centralized approach. These solutions can have negative effects with respect to network service availability. With the aim of eliminating these potential negative effects, this paper proposes a distributed solution for the computation of new paths. The distributed solution is evaluated for management entities with different performance capabilities, and for a range of traffic patterns and load levels. Our results show that the new distributed solution significantly reduces the change assimilation time and the negative impact on the network service when it is compared to a centralized solution.

Modelling multi-gigabit PCB interconnects

The move to use high-speed serial interconnects brings new challenges to PCB design and system modelling. Using multi-format simulation, designers can make informed trade-offs and improve system cost.

The IEEE-1394 high speed serial bus

The IEEE-1394 is a new standard for a digital high-speed serial interconnect bus. It allows real-time data to be mixed with other data transfers at transmission rates of 100, 200 and 400 Mbit/s. This makes it flexible enough for applications in multimedia environments where multiple video and audio streams have to be transported between several devices simultaneously. One of the most important applications in the consumer electronics world is MPEG-2 data transport between set-top box and digital video recorder. The extremely time-critical nature of MPEG-2 requires some additional processing before it can be sent on an IEEE-1394 bus. This has led to the standardization of the audio/video layer described in this article.

Tutorial on storage technology

In stark contrast to the 25% per year increase in areal density delivered by the magnetic disk industry during the 1970s and 1980s, yearly increases today are 60%, on par with DRAM density increases. Moreover, the storage industry is also delivering substantially higher data rates, smart disk-embedded readahead and writebehind, and a new generation of high-speed serial interconnects. This industry has also embraced Redundant Arrays of Inexpensive (or Independent) Disks (RAID) technology - 1997's RAID market is expected to be 13 billion dollars. With this rapidly evolving market and technology base, parallel storage systems must evolve beyond RAID levels 1 through 5. This talk is intended for researchers and practitioners interested in current trends in storage systems. It will highlight storage technology trends, RAID technology trends, and trends toward RAID-style support for network-based parallel storage systems.