High-speed Serial Communication Research Articles

Research and Implementation of Aurora Protocol NFC System

Abstract Aurora protocol is a high-speed serial communication protocol with characteristics such as high speed, low latency, open source and free. It is widely used in application fields that require a large amount of data transmission. However, Aurora communication systems also has the problem of data loss, making flow control a challenge; This paper analyzes the problem of data loss, finds out the root cause, and designs an NFC(Native Flow Control) system for the Aurora protocol. The system uses AXI4-Stream bus for communication and solves the problem by controlling the Aurora module to send NFC PAUSE code at the sending end. At the same time, by setting a reasonable upper limit value in the flow control program, the problem of data loss caused by NFC Latency is solved, and effective flow control is achieved.

A software PAM4 clock data recovery algorithm for high‐speed serial communication

Time jitter analysis is an important means to evaluate the performance of a high-speed serial communication system. Clock data recovery (CDR) is a critical component of a high-speed serial link that recovers the reference clock from a signal for jitter analysis. Traditional studies focused on CDR technology for the non-return-to-zero pattern based on a hardware design, but little work has been devoted to the software CDR especially for the four-level pulse amplitude modulated (PAM4) encoded data signals. This study proposes a new software algorithm to recover clocks from PAM4 signals that is capable of extracting synchronous clocks from PAM4 signals to design an ideal software phase-locked loop for clock recovery. The proposed algorithm extracts more types of data transition edges than hardware methods to avoid the loss of jitter information. Besides, the algorithm designs an ideal phase-locked loop to improve the filtering accuracy. This algorithm has been implemented in MATLAB, and shows superior performance to that of conventional CDR technology.

Design of Data Acquisition System for TOF Detectors in the CEE Experiment

The CSR External-target Experiment(CEE) system under development may reach an average data rate of 2 GB/s after being triggered. In response to the design requirements of the entire spectrometer, a generic stream processing data acquisition architecture D-Matrix is put forward in the article, and a specific scheme of D-Matrix in the Time-of-Flight detector(TOF) subsystem is proposed. The DAQ of the TOF system uses high-speed serial communication methods such as optical fiber and PCIe bus to complete data transmission from Front-End Electronics(FEE) to the servers, and deploys and cascades stream processing nodes with a unified interface to complete event building, command routing, Real-time status monitoring and displaying and data storage tasks. In addition, the DAQ of the TOF system has strong versatility in hardware and logic design, it also can be compatible with other sub-detector systems, and can be further applied to the global system of CEE experiments.

Development of Next-Generation Timing System for the Japan Proton Accelerator Research Complex

A precise and stable timing system is necessary for high intensity proton accelerators such as the J-PARC. The original timing system, which was developed during the construction period of the J-PARC, has been working without major issues since 2006. After a decade of operation, the optical modules, which are key components for signal transfer, were discontinued already. Thus, the next-generation timing system for the J-PARC has been developed and built. The new system is designed to be compatible with the original system in terms of the operating principle. The new system utilizes modern high speed serial communication for the transfer of the clock, reference trigger, and type code. We describe the system configuration of the next-generation timing system and current status.

Serial Rapid IO high speed optical interface protocol for Indigenous MRI

This paper presents the available literature on high speed Serial Rapid Input Output communication protocol. The MRI gradient amplifier system consists of a cabinet with a power supply and three Gradient Amplifiers. It is a three axes Gradient Amplifier system, which can be used in a MRI system to control the X, Y and Z Gradient Coils.  The optical interface this current setpoint can be transmitted digitally to the Gradient Amplifier. The gradient amplifier system possess optical interface which is a high speed interface intended for communication of current setpints, system clock, control diagnostics by the MRI system host. This optical interface benefits from digital optical isolation and removes cable, conversion loses and noise on the current setpoint.

Evaluation of a high-throughput communication link for future automotive ADAS controllers

The trend toward further integration of automotive electronic control units functionality into domain control units as well as the rise of computing-intensive driver assistance systems has led to a demand for high-performance automotive computation platforms. These platforms have to fulfill stringent safety requirements. One promising approach is the use of performance computation units in combination with safety controllers in a single control unit. Such systems require adequate communication links between the computation units. While Ethernet is widely used, a high-speed serial link communication protocol supported by an Infineon AURIX safety controller appears to be a promising alternative. In this paper, a high-speed serial link IP core is presented, which enables this type of high-speed serial link communication interface for field-programmable gate array–based computing units. In our test setup, the IP core was implemented in a high-performance Xilinx Zynq UltraScale+, which communicated with an Infineon AURIX via high-speed serial link and Ethernet. The first bandwidth measurements demonstrated that high-speed serial link is an interesting candidate for inter-chip communication, resulting in bandwidths reaching up to 127 Mbit/s using stream transmissions.

Design Scheme of Communication Node Based on FlexRay Bus

As a high-speed and reliable serial communication bus, the FlexRay bus has gradually become the mainstream of vehicle network systems. In order to verify the feasibility of the bus technology in aerospace applications, this paper designs a FlexRay communication node based on TI's high-performance microcontroller TMS570LS3137 for security systems. In the whole system, with the DSP of core, the FlexRay communication protocol is achieved by using the bus controller TJA1080 to carry out data transmission. This method is suitable for data transmission of pint and medium-sized UAV (unmanned air vehicles) flight control system with high integration and high transmission rate.

Adaptive Transmit-Side Equalization for Serial Electrical Interconnects at 100 Gb/s Using Duobinary

The ever-increasing demand for more efficient data communication calls for new, advanced techniques for high speed serial communication. Although newly developed systems are setting records, off-line determination of the optimal equalizer settings is often needed. Well-known adaptive algorithms are mainly applied for receive-side equalization. However, transmit-side equalization is desirable for its reduced linearity requirements. In this paper, an adaptive sign–sign least mean square equalizer algorithm is developed applicable for an analog transmit-side feed-forward equalizer (FFE) capable of transforming non-return-to-zero modulation to duobinary (DB) modulation at the output of the channel. In addition to the derivation of the update strategy, extra algorithms are developed to cope with the difficult transmit–receive synchronization. Using an analog six tap bit-spaced equalizer, the algorithm is capable of optimizing DB communication of 100Gb/s over 1.5-m Twin-Ax cable. Both simulations and experimental results are presented to prove the capabilities of the algorithm demonstrating automated determination of FFE parameters, such that error-free communication is obtained (BER $ using PRBS9).

Application of High Speed Serial Data Transmission System in Remote Sensing Camera

In order to meet the system needs of miniaturization, real-time, high-speed data and high reliability transmission in remote sensing camera, a high-speed serial protocol based on high-speed serial/parallel converter SerDes is proposed. For the SerDes high-speed serial data transmission chip for the physical layer, FPGA for the link layer of the communication system, design high-speed serial transmission communication protocol. Through the development of a simplified protocol for the upper user to provide a simple data interface. The system completed the data rate of 12.5Gbps point to point high-speed transmission. Verification is done by sending a pseudo-random code between boards. System work 3 hours, the measured bit error rate is less than 10 -12 .

Platform Independent Implementation of High Speed Serial Communication Based on FPGA

In various embedded system applications, the high speed multi-serial communication is necessary. Various embedded systems require DSP (Digital Signal Processing) to process information & FPGA to control the peripheral devices. UART (Universal Asynchronous Receive Transmit) is designed in FPGA & connected to DSP so as to meet the real time capability of system along with compact, stable & reliable data transmission. In this paper we propose a software-implementation technique of an UART to get a platform independent UART-core for high speed serial communication in FPGA. Here the core is written in Verilog & implemented using XILINX ISE.

A Circuit to Eliminate Serial Skew in High-Speed Serial Communication Channels

This brief relates to communication established through high-speed serial links. A serial communication channel can be formed by grouping multiple high-speed serial communication lanes to achieve greater serial bandwidth. Such channels require circuitry to eliminate relative skew across multiple lanes to ensure data integrity in the receiver. Channel bonding is a mechanism used to synchronize serial communication channels in larger data rate and bandwidth applications. This brief presents an approach to channel bonding that optimizes area, power, and initialization time and yields better performance. The ideas discussed here use a delay-based model and explore the possibility of performing channel bonding in a centralized way. The methodology is deployed in the Aurora Protocol Solution Suite, and a comparative analysis with another state-of-the-art approach is performed.

단일 핀을 이용한 직렬 통신 설계 및 구현에 관한 연구

최근 가전제품, 모바일 장비, 웨어러블 컴퓨터 등의 IoT 분야에서 센서 정보를 주고 받는 직렬 통신 방식이 사용된다. 기존의 SPI와 I2C 직렬 통신 방식은 클럭과 데이터 2개의 핀을 사용하여 비교적 빠른 속도로 데이터를 전송하는 방식이다. 사용되는 사물들이 점차 작아지고, 데이터 전송 정보의 양이 적어지면서 전송 속도보다는 하드웨어의 단순화가 중요한 설계요소가 되는 응용분야가 늘어나고 있다. 본 논문에서는 단일 핀을 사용하여, 데이터를 직렬로 송 수신하는 회로를 설계하고 FPGA로 구현하였다. 제안된 단일 핀 직렬 통신 프로토콜은 적은 양의 데이터를 저속으로 통신하는 IoT 제품에 적합하다. It has been increased that communicate each other things such as consumer electronics, mobile equipments and wearable computer with serial communication protocol. The conventional method of SPI and I2C high speed serial communication is widely used with 2 pin of clock and data pin. It has been more important than the speed of data transfer to simplify the hardware structure because the IoT components is reduced the hardware complexity. In this paper, we describe the protocol and implementation of serial data transfer with only one pin. The proposed protocol is suitable for the mobile products that send and receive the small amount of data with low speed and low power consumption.

A switchable high-speed fiber-optic ring net topology and its method of high-performance synchronization for large-capacity power electronics system

With the particularity in the structures of large-capacity power electronics converter devices, the high-speed serial fiber-optic ring net communication control mode has gradually superseded the conventional centralized control mode. However, this fiber-optic ring net cannot accurately synchronize all the nodes in the system easily due to its own network delay and data retransmission, and even the net requires a more complex communication protocol for its operation. To solve these problems, this paper has conducted an investigation into the proposed switchable high-speed fiber-optic ring net, made a simple and feasible communication protocol and presented a method of high-performance synchronization based on the sequence observer. The synchronization method can be used to achieve the synchronization accuracy within 8ns, thus overcoming the low accuracy and the accumulation of delay errors that exist in the current synchronization methods. As a result, the accurate synchronization of the whole system has been fulfilled. Finally, The results obtained from the data communication and synchronization performance experiments and the system’s trial run have verified the correctness, feasibility and superiority both the developed communication protocol and the proposed synchronization method.

A Regulator Design for a SerDes PHY of a High Speed Serial Data Interface

A fully integrated 3.3 V-to-1.2 V supply voltage regulator for application in IEEE 1394B PHY has been designed in 0.13μm SMIC Mixed Signal process technology. The regulator is able to deliver peak current transient of 300 mA, while the output voltage remain within a margin of 10% around the nominal value. The PSRR response larger than 52 dB for frequencies up to 10 kHz under the condition of IL=300 mA. The FOM of the circuit can be better than 2.5. The circuit can be used in all types of high speed serial data communication system. Index Terms—On-chip voltage regulator, IEEE 1934B PHY, class-AB.

An Automatic Synchronization Method for Distributed Power Electronics System

Currently, the high-speed serial fiber-optic ring net communication is a main method for performing the distributed control network topology and control mode. Because of a network transmission delay inherent in the topology, synchronization between nodes has become a critical issue which needs to be studied. The existing synchronization methods largely depend on the complex communication protocol. Therefore, this paper has proposed a method of automatic measurement and compensation of synchronization delay, and analyzed its operating principle and implementation procedure in detail. The results obtained from the experiments prove the proposed method to be correct, effective and practicable.

2-step DPC를 이용한 이중루프 DLL기반의 광대역 클록 데이터 복원회로 설계

A recovered jitter of CDR(Clock and Data Recovery) Circuit based on Dual-loop DLL(Delay Locked Loop) for data recovery in high speed serial data communication is changed by depending on the input data and reference clock frequency. In this paper, 2-step DPC which has constant jitter performance for wide-range input frequency is proposed. The designed prototype 2-step CDR using proposed 2-step DPC has operation frequency between 200Mbps and 4Gbps. Average delay step of 2-step DPC is 10ps. Designed CDR circuit was tested with 0.18um CMOS process.

FlexRay 게이트웨이를 이용한 차량용 통합 네트워크 구현

FlexRay는 차세대 차량 내 전자 장치간의 통신을 위해 고속의 시리얼 통신, time triggered bus, fault tolerant 통신을 제공하는 새로운 네트워크 통신 시스템의 표준이다. FlexRay는 CAN에 비하여 전송속도 최소 10배 이상이며, 수동 버스 토폴로지뿐만 아니라 능동 스타 토폴로지 구성이 가능하다. 본 논문에서는 MC9S12XF512 마이크로콘트롤러를 이용하여 FlexRay 모듈을 구현하고 CAN 메시지를 변환하여 전송할 수 있도록 게이트웨이를 구현하였다. 실험을 통하여 구현한 보드가 성공적으로 동작함을 확인하였다. FlexRay is a new standard of network communication system which provides a high speed serial communication, time triggered bus and fault tolerant communication between electronic devices for future automotive applications. The speed of FlexRay is 10 times higher than that of CAN. In this paper, FlexRay module is implemented using MC9S12XF512 micro-controller and gateway converting CAN message to FlexRay message. It is shown that the implemented system operates successfully.

자동차 네트워크 시스템을 위한 FlexRay 드라이버 개발

As the demands for the safety and convenience applications of the vehicles increase, the data load for the In-vehicle Network has increased significantly. As a result, a deterministic and fault-tolerant communication system is required to implement the safety critical applications such as X-by-wire systems. FlexRay communication system is a new standard of network communication system which provides the high speed serial communication, time triggered bus and fault tolerant communication between electronic devices. In addition to time-triggered communication, as providing of the event-triggered communication such as CAN, FlexRay protocol is able to manage the restricted communication resource more effectively. This paper presents the development of FlexRay driver which will be applied to the future ECU's communication system. To develop the FlexRay driver, the FlexRay requirement specification and FlexRay specification is analyzed. The developed FlexRay driver is implemented by using MPC5567 microprocessor of the Freescale semiconductor. To verify the developed FlexRay driver, the waveform of the FlexRay driver was measured and compared with the CAN communication system. As a result, the bus load is reduced about 13% compared with the CAN communication system.

Design of FlexRay Communication Network Using Active Star

FlexRay is a new standard of network communication system which has been developed for future automotive applications. It was devised by automotive manufacturers and semiconductor vendors. FlexRay provides a high speed serial communication, time triggered bus and fault tolerant communication between electronic devices for automotive applications. In this paper, FlexRay system is first designed using SDL (Specification and Description Language). For hardware implementation, FlexRay system is designed using Verilog HDL based on the SDL design result. The disigned system is synthesized using Synopsys Design Compiler with the Hynix 0.18 ?m cell library. For constructing a FlexRay communication network, the active is used since active star systems can provide high speed data transmission up to 10 Mbps. The performance of the active star network is tested using one transmitter node and two receiver nodes.

The Modular Multisensory DLR-HIT-Hand: Hardware and Software Architecture

This paper presents hardware and software architecture of the newly developed compact multisensory German aerospace research (DLR)-Harbin Institute of Technology (HIT)-Hand. The hand has four identical fingers and an extra degree of freedom for the palm. In each finger, there is a field-programmable gate array (FPGA) for data collection, brushless dc motors for control, and communication is accomplished with palm's FPGA by point-to-point serial communication (PPSeCo). The kernel of the hardware system is a peripheral component interconnect (PCI)- based high-speed floating-point DSP for data processing, and FPGA for high-speed (up to 25 Mb/s) real-time serial communication with the palm's FPGA. In order to achieve high modularity and reliability of the hand, a fully mechatronic integration and analog signals in situ digitalization philosophy is implemented to minimize the dimension and number of the cables (five cables including power supply), and protect data communication from outside disturbances. Furthermore, according to the hardware structure of the hand, a hierarchical software structure has been established to perform all data processing and the control of the hand. It provides basic air position indicator (API) functions and skills to access all hardware resources for data acquisition, computation, and teleoperation. With the nice design of the hand's envelop, the hand looks more like a humanoid.