High-speed Packet Switching Research Articles

HP4 High-Performance Programmable Packet Parser

Now, header parsing is the main topic in the modern network systems to support many operations such as packet processing and security functions. The header parser design has a significant effect on the network devices' performances (latency, throughput, and resource utilization). However, the header parser design suffers from a lot number of difficulties, such as the incrementing in network throughput and a variety of protocols. Therefore, the programmable hardware packet parsing is the best solution to meet the dynamic reconfiguration and speed needs. Field Programmable Gate Array (FPGA) is an appropriate device for programmable high-speed packet implementation. This paper introduces a novel FPGA High-Performance Programmable Packet Parser architecture (HP4). HP4 automatically generated by the P4 (Programming protocol-independent Packet Processors) to optimize the speed, dynamic reconfiguration, and resource consumption. The HP4 shows a pipelined packet parser dynamic reconfiguration and low latency. In addition to high throughput (over 600 Gb/s), HP4 resource utilization is less than 7.5 percent of Virtex-7 870HT, and latency is about 88 ns. HP4 can use in a high-speed dynamic packet switch and network security.

HP4 High-Performance Programmable Packet Parser

Now, header parsing is the main topic in the modern network systems to support many operations such as packet processing and security functions. The header parser design has a significant effect on the network devices' performances (latency, throughput, and resource utilization). However, the header parser design suffers from a lot number of difficulties, such as the incrementing in network throughput and a variety of protocols. Therefore, the programmable hardware packet parsing is the best solution to meet the dynamic reconfiguration and speed needs. Field Programmable Gate Array (FPGA) is an appropriate device for programmable high-speed packet implementation. This paper introduces a novel FPGA High-Performance Programmable Packet Parser architecture (HP4). HP4 automatically generated by the P4 (Programming protocol-independent Packet Processors) to optimize the speed, dynamic reconfiguration, and resource consumption. The HP4 shows a pipelined packet parser dynamic reconfiguration and low latency. In addition to high throughput (over 600 Gb/s), HP4 resource utilization is less than 7.5 percent of Virtex-7 870HT, and latency is about 88 ns. HP4 can use in a high-speed dynamic packet switch and network security.

Tolerable performance of silicon photonic optical-serial-to-parallel converter with variable power splitter.

We have proposed and investigated the tolerable performance of an optical serial-to-parallel converter with phase operation (OSPC) with lower power consumption than the conventional scheme for the purpose of achieving reduction of both the processing load and the processing latency of the high-speed packet switching systems in the data center. The target OSPC consists of Mach-Zehnder delay interferometers (MZDIs) and balanced photodetectors with silicon (Si) photonic technology. However, we have confirmed that the performance becomes degraded due to optical propagation losses of the delay lines in MZDIs. To solve this issue, unbalanced splitting ratio of a multi-mode interferometer (MMI)-type couplers in the MZDIs has been investigated, but we have found the necessity of improving the tolerance of the splitting ratio deviation. In this paper, we will analytically and experimentally demonstrate the improvement of the characteristics by using an OSPC with variable splitting ratio optical coupler (VSOC) consisting of a symmetric Mach-Zehnder interferometer (MZI). By observing the transmission spectra of the device with various applied voltage to the heater, controllability of peak-to-valley ratios of transmission spectra was observed. In addition, splitting ratio of the output symmetric MMI almost matches well with that of the optimized peak-to-valley ratios of transmission spectra by using short-optical pulse injection. We have confirmed the tolerable performance of the Si-photonic OSPC by using VSOC with the symmetric MZI.

High-speed Optical Packet Switching for Photonic Datacenter Networks

High-speed Optical Packet Switching for Photonic Datacenter Networks

Packet Switch Scheduler for Increasing Sending Packet

Recently, the need of the high speed packet switch is increased. The Re-2DRR scheduling algorithm based on 2DRR scheduling algorithm provides high throughput communication on a packet switch. However, computer network is using many cases, that huge data communication, complex, and other. This paper proposes a new method to increase choices in algorithm variation for three specific systems and more easily implementation than Re-2DRR. The effectiveness of the proposed algorithm is shown through simulation studies.

MODELLING THE PERFORMANCE OF CLASS-BASED WEIGHTED FAIR QUEUE USING OPNET

Congestion control and internet network resources management are complex and critical issues in a high-speed packet switch data network, due to the emergence growth of modern multimedia streaming services. The increasing number of computer users in various organizations and institutions of higher learning have spurred a great deal of research on network traffic control. Network administrators are facing the challenges of providing efficient services that can satisfy user requirements. This research study proposed queuing algorithm based on classbased weighted fair queue scheme to complement congestion. Network simulation environment are designed and modeled using OPNET simulation software in-order to overcome the limitation of the traditional queuing approach. Various simulations scenarios are conducted. Analysis comparison with first-in-first-out and priority queue is recorded. And also, various network traffics such as: HTTP, video conferencing and voice applications among others are considered. From the graphical results obtained clearly shows that the overall applications services performances optimize significantly. In terms of the throughput, packet loss and queuing delay, the algorithms performs excellently compared with the FIFO and priority queue. This paper examines the implication of queuing scheduling algorithms on an IP router. It also outlines the effectiveness of the proposed algorithm in managing network resources during the period of congestion.

Asynchronous vs synchronous input-queued switches

Input-queued (IQ) switches are one of the reference architectures for the design of high-speed packet switches. Classical results in this field refer to the scenario in which the whole switch transfers the packets in a synchronous fashion, in phase with a sequence of fixed-size timeslots, tailored to transport a minimum-size packet. However, for switches with large number of ports and high bandwidth, maintaining an accurate global synchronization and transferring all the packets in a synchronous fashion is becoming more and more challenging. Furthermore, variable size packets (as in the traffic present in the Internet) require rather complex segmentation and reassembly processes and some switching capacity is wasted due to partial filling of timeslots.Thus, we consider a switch able to natively transfer packets in an asynchronous fashion thanks to a simple and distributed packet scheduler. We investigate the performance of asynchronous IQ switches with different queueing architectures (one queue per input and one queue for input–output pairs) and show that, despite their simplicity, their performance is comparable or even better than those of synchronous switches. We highlight the peculiar role of the variation coefficient of the packet length. Finally, for synchronous switches we evaluate the actual bandwidth overhead due to packet segmentation, by considering a large set of traffic traces covering the period 2008–2013. We show that an impressive amount of bandwidth (up to 30%) can be lost due to segmentation, even if the internal cell size is optimally chosen.These results demonstrate the potential interest of the asynchronous approach in the design of high-performance switches.

A Packet Switch Scheduler based on 2DRR for High-Throughput

Recently, the need of the high speed packet switch is increased. The basic 2DRR scheduling algorithm provides high throughput, fair access and simple working on a packet switch. However, few input and output node could not be permissioned in some timeslots. It occurs decreasing throughput and some transmission delay. This paper proposes a new packet switch scheduling algorithm. The proposed scheduling algorithm provides higher throughput and low delay. The effectiveness of the proposed algorithm is shown through simulation studies.

Packet QoS level classifier based on optical binary priority comparison

Next generation High-Speed optical packet switching networks require components capable of classifying incoming packet into the appropriate priority queue according to the service class of the packet. For the first time, we proposed an all-optical packet QoS (Quality of Service) level classifier employing a sequential binary packet priority comparator, which is implemented using the SOA-based optical logic gates. The performance of the optical binary packet priority comparator was verified experimentally at 1 Gbit/s showing that the proposed scheme can operate higher data rates. These packet level classifier structures are attractive for all-optical network and applications.

Multihop Control Schemes in Switches With Reconfiguration Latency

Optical switching fabrics (OSFs) are receiving increasing attention in the design of high-speed packet switches, due to their excellent properties in terms of available bandwidth and reduced power consumption. However, for most optical devices, the latency needed to reconfigure input/output switch port connections may not be negligible with respect to the packet transmission time and can adversely affect switch performance, creating high delays and reduced throughput. We consider OSFs, and we propose a multihop approach to schedule packet transfers; i.e., packets are sent to the final destination port by exploiting transmission through intermediate ports. We show that the multihop approach is a promising technique to control the trade-off between delay and throughput, and it permits us to partly decouple the switch reconfiguration rate from the packet duration. We propose a general framework to solve the issue of multihop transmission in input-queued packet switches. Furthermore, we examine the multihop approach when the direct exchange of packets among ports is based on multidimensional regular topologies. We discuss which sequence of intermediate ports should be traversed to reach the final output port (i.e., the internal routing) and the switch time-scheduling problem (i.e., when a pair of ports can exchange packets). Performance is analyzed both analytically and by simulation.

All-optical router with pulse-position modulation header processing in high-speed photonic packet switching networks

In future high-speed photonic packet switching networks, it is highly desirable to carry out robust all-optical header recognition to provide high-throughput routing. The authors present a pulse-position modulation header processing (PPM-HP) scheme, offering significantly reduced routing table size and employing a single bit-wise AND operation to carry out correlation of the packet header with the entire routing table entries. The downsized routing table also offers multiple transmission modes (unicast, multicast and broadcast) in the optical layer and improves core network scalability where the number of core/edge nodes could be altered without the need for changing the number of routing table entries. The authors present modelling and simulation of the packet switching router based on PPM-HP. Noise propagation and crosstalk incurred in a multiple-hop routing scenario are investigated. The simulation results are presented and compared with the theoretical calculations.

Trends in highly scalable crossbar-based packet switch architecture

A combined input and crosspoint queued (CICQ) switch is receiving significant attention to be the next generation high speed packet switch for its scalability; however, a multi-cabinet implementation of a combined input and crosspoint queued (CICQ) switch unavoidably introduces a large round-trip time (RTT) latency between the line cards and switch fabric, resulting a large crosspoint (CP) buffer requirement. In this paper, virtual crosspoint queues (VCQs) that significantly reduces the CP buffer requirement of the CICQ switch is investigated. The VCQs unit resides inside the switch fabric, is dynamically shared among virtual output queues (VOQ) from the same source port, and is operated at the line rate, making the implementation practical. A threshold-based exhaustive round-robin (T-ERR) arbitration is employed to reduce buffer hogging at VCQ. The T-ERR at VCQ and CP arbiters serves packets residing in a longer queue more frequently than packet residing in a shorter queue. Consequently, the T-ERR, drastically increases the throughput of the CICQ switch with small CP buffers. A multi-cabinet implementation of CICQ switch do not support multicasting traffic well since a combination of small CP buffer in the switch fabric and a large RTT latency between the line cards and switch fabric results in non-work conservation of the intra-switch link. Deployment of multicast FIFO buffer between the input buffer and CP buffer shows a promise. With its ability to achieve high throughput independent of RTT and switch port size, the integration of the VCQ architecture and T-ERR scheduler to the CICQ switch is ideal for supporting ever-increasing Internet traffic that requires higher data rate, larger switch size, and efficient multicasting.

Efficient Multicast Support in High-Speed Packet Switches

The tremendous growth of the Internet coupled with newly emerging applications has created a vital need for multicast traffic support by backbone routers and ATM switches. Considerable research work has been done on Input Queued (IQ) switches to handle multicast traffic flows. Unfortunately, all previously proposed solutions were of no practical value because they either lack performance or were simply too complex to implement. Internally Buffered Crossbar (IBC) switches, where a limited small amount of memory is added in each crosspoint of the crossbar fabric, on the other hand, have been considered as a robust alternative to buffer-less crossbar switches to improve the switching performance. However, very little has been done on multicasting in IBC switches. In this paper, we fill this gap and study the multicasting problem in IBC switches. In particular, we propose a novel IBC based multicast architecture along with a simple scheduling scheme named Multicast cross-point Round Robin (MXRR). Our scheme was shown to handle multicast traffic more efficiently and far better than all previous schemes for both the multicast FIFO architecture as well as the multicast k FIFO queues architecture. Yet, MXRR is both practical and achieves high performance.

Passive and active optical bit-pattern recognition structures for multiwavelength optical packet switching networks

Next generation High-Speed optical packet switching networks require components capable of recognising the optical header to enable on-the-fly accurate switching of incoming data packets to their destinations. This paper experimentally demonstrates a comparison between two different optical header recognition structures; A passive structure based on the use of Fiber Bragg Gratings (FBGs), whereas the active structure employs Opto-VLSI processors that synthesise dynamic wavelength profile through digital phase holograms. The structures are experimentally demonstrated at 10Gbps. Performance comparison between the two structures is also discussed. These optical header recognition structures are attractive for multiwavelength optical network and applications.

Providing service guarantees in high-speed switching systems with feedback output queuing

We consider the problem of providing per-customer service guarantees in a high-speed packet switch typically situated at the edge between a set of customers and a service provider network. As basic requirements, the switch should be scalable to high speeds per port, a large number of ports, and a large number of customers (macroflows) with independent guarantees. Existing scalable solutions are based on virtual output queuing, which is computationally complex when required to provide service guarantees for a large number of macroflows. We present a novel architecture for packet switching that provides support for such service guarantees. A cost-effective fabric with small external speedup is combined with a feedback mechanism that enables the fabric to be virtually lossless, thus avoiding packet drops indiscriminate of macroflows' behavior. Through analysis and simulation, we show that this architecture provides accurate support for service guarantees, has low computational complexity, and is scalable to very high port speeds.

OPSnet: design and demonstration of an asynchronous high-speed optical packet switch

This paper presents the results of the optical packet switched network (OPSnet) project, which investigated the design of an asynchronous optical packet switch suitable for the core of an optical transport network (OTN). The requirements for the switch were to control and route variable-length packets transmitted at bit rates beyond 100 Gbit/s. The subsystems and techniques used are analyzed and presented. Fast header encoding and passive decoding is based on the differential phase-shift keying (DPSK) method. The dual-pump four-wave mixing (d-p FWM) wavelength-conversion technique, in combination with an arrayed waveguide grating (AWG), is utilized for packet switching. An advanced and fully controllable mechanism for the packet-switch control is presented, which is implemented on field programmable gate array (FPGA) technology. The control wavelength is generated using a tunable laser, the actual wavelength and new header values are provided utilizing fast header recognition and look-up tables. The integration of the subsystems is discussed, and the results of a four-output port asynchronous packet-switch demonstrator operating at 40 Gbit/s are presented. Finally, the switch limitations are examined and design issues are discussed.

Performance of a new bus assignment algorithm for an ATM switch fabric

This paper presents the results of the performance evaluation, through analytical and simulation models, of a High Speed Packet Switch with a New Bus Assignment Algorithm, designed and developed at the Research and Advanced Studies Center of National Polytechnic Institute in Guadalajara, México (CINVESTAV-GDL). The analytical model is tested under two different arrival processes: Binomial and Poisson distributions. The simulation model is tested with two bus assignment algorithms: Fixed Start and Rotated Start . The performance parameters considered are: Cell Loss Rate, Delay and Throughput.

Concurrent fault detection for a multiple-plane packet switch

In high-speed and high-capacity packet switches, system reliability is critical to avoid loss of huge amounts of information and retransmission of traffic. We propose a series of concurrent fault-detection mechanisms for a multiple-plane crossbar-based packet switch. Our switch model, called the m+z model, has m active planes and z spare planes. This switch has distributed arbiters on each plane. The spare planes, used for substitution of faulty active ones, are also used in the fault-detection mechanism, thus providing fault detection and fault location for all switching planes. Our detection schemes are able to detect a single fault quickly without increasing transmission overhead. The proposed schemes can be used for switches with different numbers of active planes and a small number of spare planes.

Broadband packet switch processor

This paper presents an overview of the architecture for a broadband, high-speed packet switch processor used in the TRW Gen*Star system. The first application of the Gen*Star design is the Astrolin...

A new shared-buffer packet switch in ATM networks

To improve overall cell loss rate and fairness problem in shared-buffer switches, a new output-queued shared-buffer switch is proposed in this paper. In the proposed shared-buffer switches, a novel structure of output queues is used to improve the behavior of cell loss rate and resolve the fairness problem. Performance of the proposed output-queued shared-buffer switch is analyzed and compared. According to the analyzed results, the proposed shared-buffer switches show superior performance and overcome the fairness problem. Besides, the proposed buffer architecture is simple to implement in the high-speed packet switches.