High-speed Low-power Circuit Research Articles

A Closed-Form Solution for the Low-Current Collector Transit Time in Group IV and Group III-V HBTs

In certain types of heterojunction bipolar transistors (HBTs), the carrier transit time associated with the base-collector (BC) space-charge region constitutes a significant contribution to the total transit time. In many compact models, the low-current BC transit time is lumped in with the total low-current transit time and often assumed to be constant—dependent only on the collector width and material saturation velocity. This assumption, however, is insufficient for modeling high-voltage Si-based HBTs as well as for III-V HBTs, where the negative differential mobility (NDM) effect can become relevant in high-speed low-power circuits. This paper presents a closed-form solution for the low-current collector transit time based on a novel accurate analytical velocity-field formulation, covering both group IV and group III-V semiconductor materials. The new solution includes the NDM effect and is suitable for implementation in compact models, and its relevance and accuracy are demonstrated for both TCAD simulated and measured data.

Novel concept for reducing the power consumption of look ahead carry adder circuit by using stackiabatic technique

For many years, designing of the high speed low power circuits with CMOS technology was a difficult challenge for the research community. There are various levels at which design problem related to low power and increased demand can be addressed; these levels are – software level, architecture level, algorithm level, circuit level and process technology level. In this paper, we have designed a four-bit look ahead carry adder using CMOS technology. The objective of this paper is to search for different approaches that will reduce the consumption of power of look ahead carry adder. We have designed look ahead carry adder using stackiabatic technique and compared with conventional, adiabatic and stacking techniques.

Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices

This paper investigates the feasibility of sub-0.2 V high-speed low-power circuits with hetero-channel MOSFET and emerging Tunneling FET (TFET) devices. First, the device designs and characteristics of hetero-channel MOSFET and TFET devices are discussed and compared. Due to the significant leakage current of ultra-low VT hetero-channel MOSFET devices, assist-circuits are required for hetero-channel MOSFET-based circuits to operate at 0.2 V. Second, the delay, dynamic energy and the Standby power of hetero-channel TFET-based and MOSFET-based logic circuits including Inverter, NAND, BUS Driver, and Latch are analyzed and evaluated. The results indicate that hetero-channel TFET-based circuits with Dual Oxide (DOX) device design to reduce the Miller capacitance provide the potential to achieve high-speed low-power operation at VDD=0.2 V, while the use of assist-circuits in MOSFET-based design improves the delay and dynamic energy at the expense of increased device count, circuit area, and large Standby and sleep-mode leakage power. Finally, the impacts of temperature and process variations on TFET-based and MOSFET-based logic circuits are discussed.

ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics

ASIC design of a high speed low power circuit for factorial calculation of a number is reported in this paper. The factorial of a number can be calculated using iterative multiplication by incrementing or decrementing process and iterative multiplication can be computed through parallel implementation methodology. Parallel implementation along with Vedic multiplication methodology for calculation of factorial of a number ensures significant reduction in propagation delay and switching power consumption due to reduction of stages in multiplication process, in comparison with the conventionally used Vedic multiplication methodologies like ‘Urdhva-tiryakbyham’ (UT) and ‘Nikhilam Navatascaramam Dasatah’ (NND) based implementation methodology. Transistor level implementation was carried out using spice specter with standard 90nm CMOS technology and the results were compared with the above mentioned conventional methodologies. The propagation delay for the calculation of 4-bit factorial of a number was only ∼42.13ns while the power consumption of the same was ∼58.82mW for a layout area of ∼6mm2. Improvement in speed was found to be ∼33% and ∼24% while corresponding reduction of power consumption in ∼34.48% and ∼24% for the factorial calculation circuitry in comparison with UT and NND based implementations, respectively.

Design of high-speed low-power differential dynamic-like static CMOS circuit families

Designing high-speed low-power circuits with CMOS technology has been a major research problem for many years. Several logic families have been proposed and used to improve circuit performance beyond that of conventional static CMOS family. Fast circuit families are becoming attractive in deep submicron technologies since the performance benefits obtained from process scaling are decreasing as feature size decreases. The delay and power calculations of both feedback-switch logic (FSL) and cascode voltage switch logic (CVSL) in terms of adder and logical design has been observed. Feedback-switch logic (FSL) is a clockless differential circuit family that is suitable for high-speed and low power because it offers fast switching, reduced capacitance and input-switching dependent activity factor without the need of clock connection. Feedback-switch logic circuit provides the output and its complement from a single side of the gate. Cascode voltage switch logic (CVSL) is a differential circuit family since it uses both true and complementary input signals and computes both true and complementary outputs. The logic function and its complement are implemented using fast NMOS networks. Thus, clockless CVSL gates offer reduced input capacitance.

Limited switch dynamic logic circuits for high-speed low-power circuit design

This paper describes a new circuit family—limited switch dynamic logic (LSDL). LSDL is a hybrid between a dynamic circuit and a static latch that combines the desirable properties of both circuit families. The paper also describes many enhancements and extensions to LSDL that increase its logical capability. Finally, it presents the results of two multiplier designs, one fabricated in 130-nm technology and one in 90-nm technology. The 130- and 90-nm designs respectively reach speeds up to 2.2 GHz and 8 GHz.

Efficient techniques in the sizing and constrained optimisation of CMOS combinational logic circuits

Two techniques are proposed which enhance the optimisation efficiency of CMOS combinational logic circuits. One uses transition times (rise and fall times) of each gate as variables of the optimisation process. The other technique uses the optimal characteristic waveform synthesising method (OCWSM) to obtain the initial guess for the optimisation process. The optimisation process, with these two techniques, can perform sizing and optimisation for circuits with a smaller fixed-delay specification than other sizing and optimisation algorithms. The circuits sized using the proposed algorithm have shown a smaller power dissipation, especially when the delay specification is small. The CPU time consumed is reasonable. High-speed low-power circuits are thus more realisable using the proposed algorithm.

High-speed low-power circuits fabricated using a submicron NMOS technology

We present results on very high-speed low-power devices and circuits fabricated using a NMOS technology scaled to submicron dimensions. These results illustrate the electrical behavior of single minimum-size devices, and present the performance of several submicron circuits, such as ring oscillators, a 3-GHz divide-by-two counter and a 90- MHz 16 × 16 multiplier.

An MSI GaAs Integrated Circuit Using Ti/W Silicide Gate Technology

Direct-coupled FET logic (DCFL) circuits with self-aligned enhancement/depletion GaAs MESFETs are the most promising candidate for developing GaAs MSI/LSI circuits. A 4×4-bit parallel multiplier was fabricated as a test vehicle to demonstrate high-speed low-power circuit performance. The circuit chip measures 1.5 mm ×1.3 mm in size and contains 168 NOR gates with 2 µm gate length enhancement/depletion FETs. To evaluate the operating speed, a full adder implemented ring oscillator was fabricated. The propagation delay per gate was in the range between 210 and 260 ps with a power dissipation of 0.36 mW/gate. 4×4-bit multiplication was performed in 3.7 ns, with a power dissipation of 97 mW at a supply voltage of 1.5 V.