High-speed Interface Circuits Research Articles

P‐8.3: A Novel Wireless Transmission System for UHD Digital Art Display

With the development of ultra‐high definition (UHD) display technology, the display system can make the picture more appealing and realistic. It is very difficult for us ordinary people to enjoy the traditional famous art works because of its expensive price and the rare amount. Compared with the traditional art works, the price of the novel UHD digital art display system is reasonable. What's more, it can provide the real sense as the realistic paintings. Besides the photo display, the customer also want the system display the UHD video. This paper presents a novel wireless transmission system based on the rk3399 chip from Rockchip with Wi‐Fi module, bluetooth module, ethernet network module and highspeed interface circuit for UHD digital art display, especially for UHD vedio. It is designed that a hardware system with smaller printed circuit board (PCB), lower power loss and lower price. Furthermore, the transmission rate is less than 300ms, which can provide an excellent watch enjoyment.

A 9.1ENOB 200MS/s Asynchronous SAR ADC With Hybrid Single-Ended/Differential DAC in 55-nm CMOS for Image Sensing Signals

A 9.1ENOB 200 MS/s asynchronous SAR analog-to-digital converter (ADC) dealing with image sensing signals is presented in this paper. The proposed ADC, designed in 55-nm CMOS process technology, can work in both single-ended and differential modes. To guarantee the ADC linearity, a symmetrical switching method is adopted. To ensure the reference accuracy when the ADC is in operation, a 1.2-V on-chip quick-response LDO, which works under a 2.5-V supply, is also integrated. To overcome the need for a clock-generation circuit and avoid a high-speed interface circuit design, asynchronous clock logic is chosen. In addition, the comparison cycle is adjusted dynamically to guarantee the DAC settling and improve the ADC throughput. In the differential operation mode, the proposed SAR ADC exhibits a peak signal-to-noise-and-distortion ratio (SNDR) of 56.5 dB and a peak spurious-free-dynamic-range (SFDR) of 68 dB with the Nyquist input, at a 200-MS/s output rate. The ADC consumes 2.74 mW, resulting in a figure-of-merit (FOM) of 25-fJ/conversion-step. Meanwhile, in the single-ended mode, the SNDR and SFDR of the ADC are 53and 64 dB, respectively. And the power consumption is 2.25 mW, resulting in an FOM of 31-fJ/conversion-step. The area of the proposed ADC is $280\times 380\,\,\mu \text{m}^{2}$ and the ADC core occupies an active area of only $140\times 250\,\,\mu \text{m}^{2}$ .

88-<formula formulatype="inline"><tex Notation="TeX">$\mu$</tex> </formula>A 1-MHz Stray-Insensitive CMOS Current-Mode Interface IC for<newline/> Differential Capacitive Sensors

The paper describes an innovative technique to implement a low-power high-speed CMOS interface circuit for differential capacitive sensors. The proposed approach comprises a capacitance to current converter providing current-summing and current-differencing capability. It also exploits an autotuning feedback loop to control the common-mode current, thereby ensuring virtually the same maximum sensitivity and measure accuracy irrespectively of the input parasitic capacitance. Therefore, the main limitation of all previous current-mode techniques is nearly eliminated. Besides, as an additional distinctive aspect, the proposed solution is suitable for both linear- and hyperbolic-type capacitive sensors. To validate the idea an interface circuit was designed in a 65-nm CMOS technology powered from a 2.5-V supply and dissipating 88- μA standby current. Measurements show that relative capacitive sensor variations up to ± 900 fF ( ± 100% of the nominal value) even in presence of a large parasitic capacitance of 2.5 pF are detected in less than 1 μs with a sensitivity of about 5 nA/fF and with an relative error lower than ± 1.5%, without requiring digital calibration.

High-speed interface circuit for differential capacitance transducers

A high-speed capacitance difference-to-sum ratio measurement circuit is presented for differential capacitance transducers. It consists of a switched-capacitor input stage, two sample-and-hold (S/H) circuits followed by voltage-to-current (V/I) converters, and a current-ratio-controlled relaxation oscillator. This circuit offers a square-wave output whose oscillation period is directly proportional to the capacitance difference-to-sum ratio of the transducers. A prototype circuit built using discrete components exhibits conversion sensitivity (period per unit capacitance difference-to-sum ratio) amounting to 400µs and linearity error as low as 0.037%. The maximum conversion time is about 160µs when the capacitance difference-to-sum ratio is 0.4.

High-speed string matching for network intrusion detection

Intrusion detection systems are promising techniques to improve internet security. A daunting challenge in the design of internet intrusion detection systems is how to perform high-speed string matching operations. This paper presents a string matching architecture, consisting of software based classifiers and hardware based verifiers. Based on incoming packet contents, the packet classifiers can dramatically reduce the number of strings to be matched and accordingly, feed the packet to a proper verifier to conduct matching. The paper presents the proposed classifier architecture and discusses the trade-offs in the classifier design. In addition, techniques, including multi-threading FSM, high-speed FSM interface circuits and interconnects for high-speed verifier implementation on FPGA platforms are discussed. Experimental results are presented to explore the trade-offs between system performance, strings partition granularity and hardware resource cost.

ESD Protection Design With Low-Capacitance Consideration for High-Speed/High-Frequency I/O Interfaces in Integrated Circuits

Electrostatic discharge (ESD) protection has been a very important reliability issue in microelectronics, especially for integrated circuits (ICs). ESD protection design for giga-Hz high-speed input/output (I/O) circuits has been one of the key challenges to implement high-speed interface circuits in CMOS technology. Conventional on-chip ESD protection circuits at the I/O pads often cause unacceptable performance degradation to high-speed I/O circuits. Therefore, ESD protection circuits must be designed with minimum negative impact to the high-speed interface circuits and to sustain high enough ESD robustness. In this paper, ESD protection design considerations for high-speed I/O circuits are addressed, and the patents related to on-chip ESD protection designs for high-speed I/O circuits are presented and discussed. Keywords: Electrostatic discharge (ESD), input/output (I/O) interface, low capacitance (low-C), power-rail ESD clamp circuit, LC resonator, LC-tank, impedance cancellation, impedance isolation, impedance matching, distributed ESD protection scheme

Latency and Power Measurements on a 64-kb Hybrid Josephson-CMOS Memory

A 64-kbit sub-nanosecond Josephson-CMOS hybrid RAM memory is being developed with hybrid high-speed interface circuits. The hybrid memory is designed and fabricated using a commercially available 0.18 mum CMOS process and NEC-SRL's 2.5 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> Nb process for Josephson junctions. The memory bit-line output signals are detected by ultra-low power, high-speed Josephson devices. The most challenging part of the memory system is the input amplifier; the performance of this amplifier is optimized by minimizing its parasitic capacitance loading. Functionality tests were reported at the ASC 2004, high-speed measurements are the focus of this paper. Most of the power dissipation in the memory system occurs in the input interface circuits. The power dissipation and delay for the interface circuit are reported. The delay time and power dissipation of the CMOS part (including drivers, decoders, and cells), which contributes most to the total access time of the hybrid memory, are measured. The relation of measurements to simulations will be presented. Plans for future designs to reduce power dissipation and latency are described.

A High-Speed 850-nm Optical Receiver Front-End in 0.18-&lt;tex&gt;$muhbox m$&lt;/tex&gt;CMOS

A high-speed optical interface circuit for 850-nm optical communication is presented. Photodetector, transimpedance amplifier (TIA), and post-amplifier are integrated in a standard 0.18-mum 1.8-V CMOS technology. To eliminate the slow substrate carriers, a differential n-well diode topology is used. Device simulations clarify the speed advantage of the proposed diode topology compared to other topologies, but also demonstrate the speed-responsivity tradeoff. Due to the lower responsivity, a very sensitive transimpedance amplifier is needed. At 500 Mb/s, an input power of -8 dBm is sufficient to have a bit error rate of 3middot10-10. Next, the design of a broadband post-amplifier is discussed. The small-signal frequency dependent gain of the traditional and modified Cherry-Hooper stage is analyzed. To achieve broadband operation in the output buffer, so-called fT doublers are used. For a differential 10 mVpp 231-1 pseudo random bit sequence, a bit error rate of 5middot10-12 at 3.5 Gb/s has been measured. At lower bit-rates, the bit error rate is even lower: a 1-Gb/s 10-mVpp input signal results in a bit error rate of 7middot10-14. The TIA consumes 17mW, while the post-amplifier circuit consumes 34 mW

A high-accuracy, high-speed interface circuit for differential-capacitance transducer

A novel high-accuracy and high-speed interface circuit based on lock-in detector is presented for differential-capacitance transducer. In the interface, the feedback capacitance rather than feedback resistance is used in the current detector to reduce the noise due to large resistance. Capacitor–array circuit proposed makes possible to cover a wide range of capacitance changes by choosing feedback capacitor close to the measurand, which results in transfer coefficient of the current sensing circuit about −1. A precision full-wave rectifier based on phase-sensitive-detector (PSD) incorporated in demodulator eliminates the effect due to threshold voltage of diode to improve the accuracy and suppress noise. A second-order low-pass filter is incorporated in demodulator, which allows high-speed and high-accuracy interface for differential-capacitance transducers. Moreover, the circuit is immune to parasitic capacitance, resistances and exciting source. It is capable of detecting the capacitance change as small as 0.005% of the total capacitance up to 16 pF with the speed higher than 5 ksps. A capacitance diaphragm pressure transducer and a standard pressure source (RUSCA 2465 piston gauge) are connected to the circuit to confirm the analysis.

Simulation and Measurements on a 64-kbit Hybrid Josephson-CMOS Memory

A 64-kbit sub-nanosecond Josephson-CMOS hybrid RAM memory is being developed with hybrid high-speed interface circuits. The hybrid memory is designed and fabricated by using commercially available 0.25 /spl mu/m and 0.35 /spl mu/m CMOS processes and the NEC (SRL) 2.5 kA/cm2 and UC Berkeley's 6.5 kA/cm2 Nb processes for Josephson junctions. In order to simulate the low-temperature CMOS circuits, 4 K CMOS device models are established by extracting from experiments. The measurements made at 4 K include static I-V characteristics, gate capacitances and source and drain capacitances. Details of the modeling are found in a companion paper in this issue. Performance of the high-speed interface circuits is optimized by minimizing the parasitic capacitance loading. Both the functional test and high-speed measurement for the interface circuit will be discussed. The whole structure of the memory, including interface circuit, decoder, memory cell, and Josephson read-out circuit is proposed and fabricated. From simulation, a total access time well below 1 ns is expected. The power for the whole system is about 32 mW at 1 GHz. Plans for further power and access time reduction are described.

A 77 K analog monolithic HEMT amplifier for high-speed Josephson-semiconductor interface circuit

We developed 0.5 μm-gate 77 K analog monolithic HEMT amplifier that is to be used in an interface from a Josephson IC to a semiconductor IC. The HEMT was built from InGaP/InGaAs/GaAs materials that provide a stable system at 77 K. The amplifier includes a differential amplifier as its first stage to cancel out ground level fluctuations in the Josephson IC, and high gain source-grounded amplifier. An output of 0.7 V p-p was obtained from a complementary input signal of 30 mV p-p, 3 Gbit/s, that was in RZ format. We successfully used this HEMT amplifier for transferring a voltage signal from 10-stack Josephson high-voltage drivers to a room temperature 50 Ω system with an amplitude of 0.7 V p-p and a clock frequency of 300 MHz.

A portable digital DLL for high-speed CMOS interface circuits

A digital delay-locked loop (DLL) that achieves infinite phase range and 40-ps worst case phase resolution at 400 MHz was developed in a 3.3-V, 0.4-/spl mu/m standard CMOS process. The DLL uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correcting multiplexers. This more easily process portable DLL achieves jitter performance comparable to a more complex analog DLL when placed into identical high-speed interface circuits fabricated on the same test-chip die. At 400 MHz, the digital DLL provides <250 ps peak-to-peak long-term jitter at 3.3 V and operates down to 1.7 V, where it dissipates 60 mW. The DLL occupies 0.96 mm/sup 2/.

Equivalent high-speed interface circuit

An equivalent high-speed interface circuit is presented. tau E, the equivalent MTITP (the minimum time interval between two pulses) of the system, is about 35 ns when being used to collect 100 kHz random signal with LR (lost ratio)=0.35%, though the MTITP of the collecting periodic signal is about 2 mu s.

A novel high-speed interface circuit saving wiring equipment

A high-speed integrated interface circuit is described, which is capable of transmitting and receiving full duplex digital signals on a twisted pair line. Thus two independent messages may be transmitted on one line at the same time. A push-pull transmitter and a differential amplifier as receiver provide a common-mode rejection of more than 1 V in either the positive or negative direction. Output signals and input threshold are compatible with ECL F100K. Compared to conventional interface transceivers this approach has the following advantages: (1) the needed number of lines and connectors is halved; (2) only one type of circuit is necessary, because both transmitter and receiver are housed in one package; (3) the reduced number of line pins leaves space for more transceiver circuits in one package.

High-speed complementary analogue-switch driver and interface circuit

The letter describes a driver circuit that can be used in a wide variety of applications. Its virtues include symmetrical complementary outputs for switching-diode bridges or f.e.t.s. In addition, the circuit provides a means of level shifting between voltage levels.