High-speed Folding Research Articles

Miura-ori, Basics for Designing its Folding Machines

Abstract. The unique property of the Miura-ori map is due to the geometric property of “the single degree of freedom”. With this, one can open a map with a single pull motion. However, due to this property, the high-speed folding machine is difficult to realized. In this presentation, author investigates the natural geometric properties of Miura-ori in detail and proposes a basic concept for designing its folding machine. Though, the result does not provide a draft of a folding machine, the basics for the design parameters is beneficial for future works.

Digital encoding calibrated unit used in 8 bit 1 GS/s folding and interpolating ADC

In high-speed folding and interpolating ADC design, an important issue is the encoding error result from the fine and coarse channel joint encoding technology. The last bit of the coarse channel only uses the last comparator of the fine channel to encode, the misjudgement of this comparator caused by offset and other non-ideal factors will lead to the encoding error of the last bit of the coarse channel and deteriorate the linearity. A digital encoding calibrated unit is presented. It utilises the lowest four comparators of the fine channel instead of one to calibrate error encoding of the comparator. An 8 bit 1 GS/s folding and interpolating ADC with this digital encoding calibrated unit is fabricated in 180 nm CMOS technology has been used to assess the validity of the calibration.

An Encoder Used in an Ultra High-Speed Folding and Interpolating ADC

High speed encoder is the key element of high speed analog-to-digital converter (ADC). Therefor the type of encoder, the type of code, bubble error suppression and bit synchronization must be taken into careful consideration especially for folding and interpolating ADC. To reduce the bubble error which may resulted from the circuit niose, comparator metastability and other interference, the output of quantizer is first encoded with gray code and then converted to binary code. This high speed encoder is verified in the whole time-interleaved ADC with 0.18 Bi-CMOS technology, the whole ADC can achieve a SNR of 45 dB at the sampling rate of 5GHz and input frequency of 495MHz, meanwhile a bit error rate (BER) of less than 10-16 is ensured by this design.

A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology

A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.

A low-kickback-noise and low-voltage latched comparator for high-speed folding and interpolating ADC

A novel low-kickback-noise Class-AB latched comparator utilizing unilateralization technique is presented for high-speed folding and interpolating analog-to-digital converter (ADC).The load transistors are independent with the clock signal. So the comparator can suppress the kickback noise significantly and work at low power supply. Dummy transistors and neutralization technique are also introduced to further reduce the noise. The comparator is simulated in 0.18-µm standard digital CMOS technology. A very low kickback noise voltage of 0.14mV is realized at the differential input voltage of 300mV.The power dissipation is about 202µW at 1.8V supply voltage, 250MHz clock frequency.

New low-Voltage fully programmable CMOS triangular/trapezoidal function Generator circuit

A versatile low-voltage CMOS circuit with a triangular/trapezoidal transconductance characteristic and independently programmable slope (keeping constant height or constant width), height (keeping constant slope or constant width), and horizontal position is presented. Simulation results using Cadence DFW-II that verify the functionality of the circuit with /spl plusmn/1.5-V supplies are presented. A chip prototype has been fabricated in a 0.5-/spl mu/m technology and experimentally verified. The circuit can find application in the implementation of high resolution, high speed folding analog-to-digital converters, in piecewise-linear approximation, and in the implementation of membership functions in analog and mixed-signal neuro-fuzzy systems.