High-speed Encoder Research Articles

Design of Low Power and High Speed Decoder and Priority Encoder using Carbon Nanotube Field Effect Transistor for Binary Content Addressable Memory Array

In this paper, design of Positive Feedback Adiabatic Logic (PFAL) based decoder and priority encoder using Carbon Nanotube Field Effect Transistor (CNTFET) for Binary Content Addressable Memory (BCAM) array is presented. The optimum set of CNTFET parameters such as number of tubes, chirality vector, pitch, dielectric constant and dielectric materials for low power and high speed encoder and decoder is used. The performance of proposed decoder and priority encoder is analyzed for average power, peak power and delay. Simulation results show that the proposed circuits outperforms compared to that of CMOS technology based circuits. The average power and peak power of the proposed decoder and priority encoder are in the range of μW while the range of values for CMOS based decoder are mW. The average delay of the proposed decoder is improved by 35.96% compared to that of CMOS based decoder. The average delay of the proposed priority encoder is improved by 30.77% compared to that of CMOS based priority encoder. All simulations are conducted for both CMOS and CNTFET based decoder and Priority encoder in HSPICE at 32 nm technology.

Fast encoding of quasi‐cyclic low‐density parity‐check codes in IEEE 802.15.3c

A high-speed encoder is proposed for quasi-cyclic low-density parity-check codes. By merging some sub-matrices of a parity-check matrix H in an approximately lower triangular form, a compact encoding process is obtained, reducing pipeline stages from six to three. Moreover, well-designed circuits are used to implement back-substitution and sparse-matrix–vector multiplication. The low-density parity-check (672, 336) code in IEEE 802.15.3c shows that the proposed encoder is easy to implement, runs fast, and requires no memory.

An Encoder Used in an Ultra High-Speed Folding and Interpolating ADC

High speed encoder is the key element of high speed analog-to-digital converter (ADC). Therefor the type of encoder, the type of code, bubble error suppression and bit synchronization must be taken into careful consideration especially for folding and interpolating ADC. To reduce the bubble error which may resulted from the circuit niose, comparator metastability and other interference, the output of quantizer is first encoded with gray code and then converted to binary code. This high speed encoder is verified in the whole time-interleaved ADC with 0.18 Bi-CMOS technology, the whole ADC can achieve a SNR of 45 dB at the sampling rate of 5GHz and input frequency of 495MHz, meanwhile a bit error rate (BER) of less than 10-16 is ensured by this design.

A 20-GS/s 5-b SiGe ADC for 40-Gb/s Coherent Optical Links

A 10-GBd 40-Gb/s coherent optical transport is a promising technology for higher data rate communications by virtue of improved sensitivity and high spectrum efficiency. One of the major challenges in designing a 40-Gb/s coherent quadrature-phase-shift-keying receiver is to achieve high-speed data conversion at around 20-GHz sampling rate with at least 5-bit resolution. With the detailed design framework for the target requirements, this paper presents a 5-bit 20-GS/s flash analog-to-digital converter (ADC) realized in 0.18-m SiGe BiCMOS technology. The ADC includes a track-and-hold amplifier (THA) incorporated with linear distortion compensation, double-interpolation preamplifier, current bias-weighted comparator, and high-speed encoder logic. At 4 V, the THA had a bandwidth that exceeded 23 GHz and an IIP3 of 24 dBm. The ADC achieves a signal-to-noise-plus-distortion ratio of 28.6 dB and a spurious-free dynamic range of 36 dB with a 1-GHz input sinusoid sampled at 20 GS/s. The ADC has a wide resolution bandwidth of 7 GHz, and the figure of merit is 9.54 pJ/conversion-step. The ADC consumes 3.24 W from 4- and 3-V supplies when sampled at 20 GHz. The prototype ADC occupies 8.68 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of silicon area.

Memory-efficient and high-speed LDPC encoder

A memory-efficient and high-speed low-density parity-check (LDPC) encoder is proposed, which uses a memory efficient parity-check matrix, called a differential parity-check matrix. The partially parallel architecture is also proposed for use in high-speed encoding. The proposed two-stage cyclic shifter is appropriate for a differential parity-check matrix and partially parallel architecture with low complexity. The proposed LDPC encoder is implemented with a 21% reduction in memory. The speed of the proposed partially parallel LDPC encoder is three times faster than the existing serial LDPC encoder.

CAVLC coding algorithm and FPGA realization of high-speed entropy encoder

Context-Based Adaptive Variable-Length Coding(CAVLC) algorithm was adopted as an entropy coding method in baseline and extended profile of H.264/AVC standard,but the detailed syntax on which was not explicitly stipulated.A profound analysis on the CAVLC coding algorithm of H.264 standard was performed based on the principle of CALVC decoding method.A high-speed and low power-consumption CAVLC coder for H.264/AVC standard was presented according to the former analysis,in which multi-clock domain processing and parallel processing techniques were adopted to improve the performance of the system,and arithmetic were used to replace some static code table to reduce memory consumption.The detailed design and FPGA realization method on each sub-blocks are also concerned.Finally,FPGA verification and realization indicates that the maximum coding system clock can up to 107.97 MHz,and the coding delay is less than 36 clock cycles,which can adequately meet the needs of some high-definition and real-time applications.

A 0.18 μm CMOS pipelined encoder for a 5 GS/s 4-bit flash analogue-to-digital converter

A high-speed CMOS encoder intended for a 5 gigasample/second (GS/s) 4-bit flash analogue-to-digital converter (ADC) is presented. To meet the speed and power targets of the ADC, low-swing signalling is used in all the internal sub-blocks of the ADC, including the encoder, which is implemented in current-mode logic (CML). To further enhance the encoders speed, two-stage pipelining is used. Details of the architecture are described. The proposed two-stage pipelined encoder as well as an encoder with no pipelining are designed and simulated in a 0.18 µm CMOS technology, and their performances are compared. Simulation results predict a 40% speed improvement for the pipelined encoder. The encoder circuit consumes 4 mW from a 1.8 V supply while operating at 5 GHz.

High speed encoder positioning with ERO

High speed encoder positioning with ERO

A field-programmable high-speed encoder for binary cyclic codes

Abstract A new algorithm is proposed in this paper for encoding an («, k) binary cyclic code using its parity polynomial. Based on this algorithm, a field-programmable highspeed encoder is also presented, capable of being programmed for encoding most of the binary block codes. Programming the new circuit and verifying the programmed result are very convenient in light of the fact that only a DC power supply and a voltage meter would be required. Furthermore, unlike the encoding circuit of Lin and Costello (1983), which was based on the parity polynomial as well, the longest propagation delay of the new encoding circuit is observed as being independent of the k such that it would be highly suitable for codes having large k.

High-speed encoder for the 16B9Q line code

A novel approach is described for the high speed implementation of a 2nB/(n + 1)Q transmission line code. Input data are processed so that the (n + l)th control symbol is available well before it is required at the end of each word. The performance of this codec scheme was verified experimentally using the 16B9Q code in a multimode optical fibre link at 44.736 Mb/s.