High-speed Digital Signal Processing Research Articles

Operation of a Ramsey-CPT microcell atomic clock with driving current-based power modulation of a VCSEL

We report on the operation of a coherent population trapping (CPT) microcell atomic clock using a pulsed Ramsey-like interrogation. The Ramsey-CPT sequence, defined by two-step optical pulses separated by a free-evolution dark time, is produced by switching on and off the output power of a low-power vertical-cavity surface-emitting laser, through direct modulation of its driving current. High-contrast and narrow Ramsey-CPT fringes are detected without the use of any external optical modulator stage. We demonstrate closed-loop operation of the clock based on high-speed digital signal processing implemented in a field programmable gate array board. The clock's short-term fractional frequency stability is 1.3 × 10−10τ−1/2 until 2000 s. A power light-shift coefficient of 8 × 10−11/μW, in relative value, is obtained for a dark time of 150 μs. This value is about ten times lower than in the continuous regime. These results show the feasibility of fully integrated atomic clocks based on Ramsey spectroscopy, which could provide enhanced long-term stability.

Development of a high-speed digital pulse signal acquisition and processing system based on MTCA for liquid scintillator neutron detector on EAST

Development of a high-speed digital pulse signal acquisition and processing system based on MTCA for liquid scintillator neutron detector on EAST

Design of A High-Precision Component-Type Vertical Pendulum Tiltmeter Based on FPGA.

This paper presents a high-precision component-type vertical pendulum tiltmeter based on an FPGA (Field Programmable Gate Array) that improves the utility and reliability of geophysical field tilt observation instruments. The system is designed for rapid deployment and offers flexible and efficient adaptability. It comprises a pendulum body, a triangular platform, a locking motor and sealing cover, a ratiometric measurement bridge, a high-speed ADC, and an FPGA embedded system. The pendulum body is a plumb-bob-type single-suspension wire vertical pendulum capable of measuring ground tilt in two orthogonal directions simultaneously. It is installed on a triangular platform, sealed as a whole, and equipped with a locking motor to withstand a free-fall impact of 2 m. The system utilizes a differential capacitance ratio bridge in the measurement circuit, replacing analog circuits with high-speed AD sampling and FPGA digital signal processing technology. This approach reduces hardware expenses and interferences from active devices. The system also features online compilation functionality for flexible measurement parameter settings, high reliability, ease of use, and rapid deployment without the need for professional technical personnel. The proposed tiltmeter holds significant importance for further research in geophysics.

An Analog EIC-PIC Receiver With Carrier Phase Recovery for Self-Homodyne Coherent DCIs

Coherent techniques, used for high-capacity optical links, conventionally use high-speed ADCs and digital signal processing, which make them power hungry. For short-reach coherent links such as data center interconnects, power consumption, form factor, cost, and latency have to be greatly reduced. Co-designed photonic and electronic integrated circuits, in the optical and electrical analog domains, respectively, can achieve these goals. In this brief, for the first time, we present integration of a silicon photonic integrated coherent receiver (ICR) front-end with an electronic carrier phase recovery chip, as a part of a complete coherent receiver solution. A phase shifter in the ICR (fabricated in a 220 nm silicon-on-insulator technology) receives feedback from the CPR chip, and the combination compensates for the time varying phase offset between the modulated signal and the unmodulated carrier in the closed loop configuration. In this proof-of-concept demonstration, we present experimental results obtained from the stand-alone ICR, and its system level integration with CPR chip, for QPSK signals. The technique can be extended to a higher-order modulation formats, such as 16-QAM, for capacity scaling. The proposed scheme is suitable for carrier-forwarded coherent links, such as polarization multiplexed carrier based self-homodyne links.

Optimization of Power and Area Using VLSI Implementation of MAC Unit Based on Additive Multiply Module

The development of Digital Signal Processors (DSPs), graphical systems, Field Programmable Gate Arrays (FPGAs)/ Application-Specific Integrated Circuits (ASICs), and multimedia systems all rely heavily on digital circuits. The need for high-precision fixed-point or floating-point multipliers suitable for Very Large-Scale Integration (VLSI) implementation in high-speed DSP applications is developing rapidly. An integral part of any digital system is the multiplier. In digital systems as well as signal processing, the adder and multiplier seem to be the fundamental arithmetic units. Problems arise when using a multiplier in the realms of area, power, complexity, and speed. This paper details a more efficient MAC (Multiply- Accumulate) multiplier that has been tuned for space usage. The proposed design is more efficient, takes up less room, and has lower latency than conventional designs. The performance of the Additive Multiply Module (AMM) multiplier is measured against that of existing multipliers, where it serves as a module in the MAC reducing area and delay.

A Procedure for Precise Determination and Compensation of Lead-Wire Resistance of a Two-Wire Resistance Temperature Detector.

A procedure for the precise determination and compensation of the lead-wire resistance of a resistance transducer is presented. The proposed technique is suitable for a two-wire resistance transducer, especially the resistance temperature detector (RTD). The proposed procedure provides a technique to compensate for the lead-wire resistance using a three-level pulse signal to excite the RTD via the long lead wire. In addition, the variation in the lead-wire resistance disturbed by the change in the ambient temperature can also be compensated by using the proposed technique. The determination of the lead-wire resistance from the proposed procedure requires a simple computation method performed by a digital signal processing unit. Therefore, the calculation of the RTD resistance and the lead-wire resistance can be achieved without the requirement of a high-speed digital signal processing unit. The proposed procedure is implemented on two platforms to confirm its effectiveness: the LabVIEW computer program and the microcontroller board. Experimental results show that the RTD resistance was accurately acquired, where the measured temperature varied from 0 °C to 300 °C and the lead-wire resistance varied from 0.2 Ω to 20 Ω, corresponding to the length of the 26 American wire gauge (AWG) lead wire from 1.5 m to 150 m. The average power dissipation to the RTD was very low and the self-heating of the RTD was minimized. The measurement error of the RTD resistance observed for pt100 was within ±0.98 Ω or ±0.27 °C when the lead wire of 30 m was placed in an environment with the ambient temperature varying from 30 °C to 70 °C. It is evident that the proposed procedure provided a performance that agreed with the theoretical expectation.

Sub-Nanosecond Digital Signal Processing of Photomultiplier Tube Response Enabling Multiphoton Counting in Raman Spectroscopy.

This paper introduces a novel approach to achieve multiple photon counting for Raman spectroscopy. The multiphoton counting process is made possible by recording and analyzing the photomultiplier tube response to each pulse of a pulsed laser in a time-resolved Raman spectroscopy system. Conventional Raman spectroscopy typically considers photon arrivals as binary events assessed by a single threshold. Hence, the conventional algorithm ignores the fact that multiple photons could arrive within the same response, sacrificing potential signal gain. In this work, a high-speed data acquisition system and multiple threshold digital signal processing counting algorithm are employed to facilitate multiphoton counting, a data processing approach that differentiates photon arrival events by amplitude and time and contributes to improved Raman detection sensitivity. The multiphoton counting algorithm enables lower concentration detection, greater sensitivity, shortens experiment duration, and improves noise rejection. Results from analyses of aqueous solutions of nitrate, isopropanol, and rhodamine 6G demonstrate the versatility and effectiveness of this algorithm. The algorithm increased system sensitivity by ∼ 2.0-, 2.0-, and 3.1-fold, compared to traditional single-threshold analyses of the same data for tests performed on nitrate, isopropanol, and rhodamine 6G, respectively. Results also demonstrated that the multiphoton counting algorithm increases the upper analysis limit for high Raman-yield compounds, shifting the saturation threshold to a higher concentration in typical concentration versus intensity calibration curves.

Design and implementation of a nano magnetic logic barrel shifter using beyond-CMOS technology

Abstract Bit manipulation plays a significant role in high-speed digital signal processing (DSP) and data computing systems, and shift and rotation operations are crucial functions in it. In general, barrel shifters are used to perform these operations effectively. Nano magnetic logic circuits are among the promising beyond-CMOS alternative technologies for the design of high-speed circuits. Most of the existing circuits that have been developed using nano magnets are combinational circuits. In this work, a barrel shifter is implemented and realised using in-plane nano magnetic logic. The proposed design is the first of its kind nano magnetic logic circuit. The nano magnetic logic circuit implementation, layout generation, simulation, and validation were performed using the ToPoliNano and ModelSim tools. The logical equivalent design was synthesised and evaluated using the Synopsys Design Compiler tool. The proposed barrel shifter was realised using majority logic has 1769037 nano magnets with a boxing area of 481 × 13104 µm2 and 3276 clock zones after optimisation with the Barycenter algorithm. The proposed barrel shifter realised using Boolean logic has 315276 nano magnets with a boxing area of 265 × 5028 µm2 and 1257 clock zones after optimisation with the Barycenter algorithm. The proposed design results demonstrate that complex systems can be developed using nano magnetic logic by combining combinational and sequential circuits.

DBF-Based Fusion Control of Transmit Power and Beam Directivity for Flexible Resource Allocation in HTS Communication System Toward B5G

The demand for satellite communication increases with digitalization and globalization in the era of 5G and beyond; therefore, research and development of high-throughput satellites (HTSs) to increase the communication capacity and improve the flexibility of satellite communication systems is underway. Additionally, digital beamforming (DBF), which can control the directivity of multiple beams through high-speed digital signal processing, has received significant attention as a technology to improve the flexibility of resource allocation with HTSs. The principal control parameters in the DBF-based HTS, including the transmission power, beam gain, and placement location of each beam, cause alterations in the positional characteristics of the total throughput in the coverage area of an HTS. However, there are no power resource allocation models with dual control of these control parameters, based on the above positional characteristic. This study clarifies the effect of such control parameters on the total throughput in the coverage area of an HTS. We demonstrate a method for improving the flexibility of resource allocation to satisfy the geographic distribution of traffic requirements by constructing a power resource allocation model with a DBF-based fusion control in the HTS communication system. We evaluated the effectiveness of our proposed method through a simulation analysis using exponential annealing.

A review on teratronics: from present state to future

Teratronics is an interdisciplinary field of Opto-and Microelectronics embracing the important features of high-speed digital signal processing, high-frequency electronics, and optics and photonics. This is one of the significant challenging fields of solid state physics and technology with the new domains of electronics industry and research. This review outlines the different field of application of terahertz wave in security, medical imaging, chemical and biological sensing and highly emerging field of wide-band telecommunications along with the development of active and passive devices. Discussion encompasses from the founding concept of THz electronics to the development and future scopes. Content of this article will also include the new aspects of terahertz technology with their present contenders in the field of security and telecommunication. Dialogue for the newly evolved devices such as nano-ring and disk transistor along with stacked quantum dots systems also included to provide a novel glimpse for deep and underlying fundamental physical mechanism. All these topics will provide a critical supervision for further innovative stages in this field.

Upgraded Fiber-Optic Sensor System for Dynamic Strain Measurement in Spallation Neutron Source

We describe an upgraded fiber-optic sensor system and its performance in measuring the dynamic strains in a mercury target of the Spallation Neutron Source (SNS). Strains result from dynamic pressure waves in the stainless-steel mercury target induced by short (~700 ns), intense (up to 23.3 kJ), high-energy (~1 GeV) proton pulses. In the upgraded sensor system, the output of each sensor head is interrogated with a compact, all-fiber based Faraday Michelson interferometer, which generates interference signals with a steady phase shift. Strain waveforms are recovered from the phase-shifted interference signals using a high-speed digital signal processing procedure developed in our previous work. We demonstrate successful measurements of dynamic strain pulses, e.g., <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$400 \mu \varepsilon $ </tex-math></inline-formula> over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$190 \mu \text{s}$ </tex-math></inline-formula> , on a recently installed SNS target using the upgraded sensor system. The measured strain waveforms are analyzed for more than 20 sensor locations and/or orientations, and provide information regarding the temporal structure of strain profiles and dependence of the strain magnitude on the proton powers of 200 – 1400 kW. The new interrogator also measures the radiation-induced-attenuation (RIA) in the optical fiber, enabling experimental investigations of RIA profiles induced by a 700-ns radiation pulse. The radiation effects on the strain measurement performance are discussed over a radiation dose range of up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${4}\times {10}^{{8}}$ </tex-math></inline-formula> Gy and an RIA compensation method is proposed. The measurements allow insight into the response of this unique piece of equipment and can be used for validation of simulations.

Design of Vedic multiplierbased FIR filter for signal processing applications

Digital Signal Processing (DSP) devices are becoming increasingly important with the introduction of multiple signal processing techniques. Vedic Multiplier is one of the most common applications for high-speed DSP deployment. This paper constitutes a significant development in the design of the FIR filter architecture based on the modified Nikhalam Sutra Vedic multiplier. In addition, the Kongestone adder is used to increase speed performance. Using Xilinx FPGA Spartan 6 with Xilinx ISE, the modified architecture of FIR filter has been simulated and synthesized for achieving optimized results. The simulation results of the proposed FIR filter architecture illustrate that it operates at least 20 percent faster than traditional multiplier-based FIR filters

Coherent Data Center Links

As link bit rates within and between data centers continue to increase, it is challenging to maintain low power consumption while accommodating ever-tighter optical link budgets. Although power consumption can be reduced by co-packaging optical transceivers with electrical switches and employing optical switching, both approaches increase losses, further compressing link budgets. Local oscillator-based coherent receivers traditionally employed for long-haul systems provide a path to higher bit rates and improved link budgets, but their power consumption is excessive owing to high-speed digital signal processing (DSP). We discuss alternative designs for coherent receivers, such as DSP-free coherent receivers and Kramers–Kronig (KK) receivers. We compare them in terms of receiver sensitivity, power consumption, and complexity.

Efficient VLSI architecture for FIR filter design using modified differential evolution ant colony optimization algorithm

PurposeThis paper aims to concentrate on an efficient finite impulse response (FIR) filter architecture in combination with the differential evolution ant colony algorithm (DE-ACO). For the design of FIR filter, the evolutionary algorithm (EA) is found to be very efficient because of its non-conventional, nonlinear, multi-modal and non-differentiable nature. While focusing with frequency domain specifications, most of the EA techniques described with the existing systems diverge from the power related matters.Design/methodology/approachThe FIR filters are extensively used for many low power, low complexities, less area and high speed digital signal processing applications. In the existing systems, various FIR filters have been proposed to focus on the above criterion.FindingsIn the proposed method, a novel DE-ACO is used to design the FIR filter. It focuses on satisfying the economic power utilization and also the specifications in the frequency domain.Originality/valueThe proposed DE-ACO gives outstanding performance with a strong ability to find optimal solution, and it has got quick convergence speed. The proposed method also uses the Software integrated synthesis environment (ISE) project navigator (p.28xd) for the simulation of FIR filter based on DE-ACO techniques.

Implementation of a 32 – bit RISC processor with floating point unit in FPGA platform

With the ever-growing trends in the latest technologies, digital signal processing is one of the known platforms which is used for many applications. RISC processor is the main element in all high-speed digital signal processing applications. The aim is to develop a RISC processor by including a single precision floating point unit in the instruction set along with other instructions and a complex multiplication instruction as it is commonly used in the DSP application. The floating-point unit is written according to the IEEE 754 standard and to introduce Vedic mathematics concept to compare and estimate the performance in terms of delay. The idea is to provide an optimized floating-point arithmetic unit and thereby provide an additional feature for the RISC processor instruction set. By using the Vedic multiplier, the delay is reduced by 55% compared to the normal array multiplier. The entire design is coded in Verilog HDL simulated on Xilinx ISE 14.7 platform.

Space-time trellis codes: Field programmable gate array approach

This paper presents an implementation of Space-time Trellis Codes for 4-state on FPGA. To reach the very high data rates provided in STTC, a lot of expensive high-speed Digital Signal Processors (DSPs) should be employed for the real time applications, while it might not be affordable. This fact has motivated in designing dedicated hardware implementations using Field Programmable Gate Array (FPGA) with low cost and power consumption. The hardware device XC3S400, family Xilinx Spartan-3, and package PQ208 are used in this project, in which the STTC encoder and decoder utilizes maximum 10% and 22% as that of available device capacity respectively. The design has been simulated and synthesized successfully in Xilinx integrated software environment.

Design of a FPGA-based controller for power and period measurement in the start range of Dalat Nuclear Research Reactor

This paper introduces a new controller module based on a high-speed field-programmable gate array (FPGA) and digital signal processing (DSP) using moving average (MA) filters for calculation of the reactor power and period at the start range of the Dalat nuclear research reactor (DNRR). The reactor power is proportional to the neutron flux in the reactor core, and the reactor period is the time that the reactor power changes by a factor of 2.718. In the control and protection system (CPS) of the DNRR, the reactor power and period have been monitored by the 8-bit microprocessor controller named BPM-107R. There are two main functions of the BPM-107R controller including 1) measurement and determination of reactor power and period and 2) generation of warning and emergency protection signals by reactor power or/and by reactor period. Those discrete signals will access to the logical processing unit of the CPS to prohibit the upward movement of control rods or to shut down the reactor. The CPS has three BPM-107R controllers corresponding to three independent neutron flux measurement equipment (NFME) channels working by logic voting “2 out-of 3”. Each NFME channel was designed for detection of neutron flux density in the full range from 1×100 to 1.2×1010 n/cm2 ×s, which is divided into two sub-ranges named start range (SR) and working range (WR). The designed FPGA-based controller module was tested using simulated signals as well as signals from the CPS in comparison with the original controller BPM-107R. The experimental results show that the characteristics and functions of the two controllers are equivalent.

SARAS CD/EoR Radiometer: Design and Performance of the Digital Correlation Spectrometer

In the currently accepted model for cosmic baryon evolution, Cosmic Dawn (CD) and the Epoch of Reionization (EoR) are significant times when first light from the first luminous objects emerged, transformed and subsequently ionized the primordial gas. The 21[Formula: see text]cm (1420[Formula: see text]MHz) hyperfine transition of neutral hydrogen, redshifted from these cosmic times to a frequency range of 40[Formula: see text]MHz to 200[Formula: see text]MHz, has been recognized as an important probe of the physics of CD/EoR. The global 21[Formula: see text]cm signal is predicted to be a spectral distortion of a few 10’s to a few 100’s of mK, which is expected to be present in the cosmic radio background as a trace additive component. Shaped Antenna measurement of the background RAdio Spectrum (SARAS) is a spectral radiometer purpose designed to detect the weak 21[Formula: see text]cm signal from CD/EoR. An important subsystem of the radiometer, the digital correlation spectrometer, is developed around a high-speed digital signal processing platform called pSPEC. pSPEC is built around two quad 10-bit analog-to-digital converters (EV10AQ190) and a Virtex 6 (XC6VLX240T) field programmable gate array, with provision for multiple Gigabit Ethernet and 4.5[Formula: see text]Gbps fiber-optic interfaces. Here, we describe the system design of the digital spectrometer, the pSPEC board, and the adaptation of pSPEC to implement a high spectral resolution (61[Formula: see text]kHz), high dynamic range ([Formula: see text]:1) correlation spectrometer covering the entire CD/EoR band. As the SARAS radiometer is required to be deployed in remote locations where terrestrial radio frequency interference (RFI) is a minimum, the spectrometer is designed to be compact, portable and operating off internal batteries. The paper includes an evaluation of the spectrometer’s susceptibility to RFI and capability to detect signals from CD/EoR.

Single Sideband Transmission Employing a 1-to-4 ADC Frontend and Parallel Digitization

Distributed data-centers have emerged as a key architecture for future optical networks. This architecture relies on power and cost-efficient high-speed fiber optical connections over distances up to 80 km which can be densely wavelength-division multiplexed (WDM) in the C-band. Recently, single-polarization single sideband (SSB) direct detection (DD) has been considered as an attractive transmission scheme for achieving data rates beyond 100 Gb/s per channel over 80 km. The advantages of SSB DD transmission includes the simple transceiver architecture and the capability of electronic dispersion compensation. However, the required digitizer's bandwidth in a single-polarization SSB transmission is around four times higher than in those of a conventional dual-polarization coherent detection system offering the same data rate. This critical issue prevents the practical implementation of high-speed SSB digital signal processing (DSP) in CMOS ASIC. To address this problem, we consider in this work a 112 GSa/s SiGe HBT BiCMOS ADC frontend. Using this ADC front-end, we experimentally demonstrate a WDM SSB DD transmission at a net data rate of 200 Gb/s per channel over 80 km while using only 14 GHz of digitizer's bandwidth which is comparable to those of a full-coherent counterpart.

FPGA Based Vector Control of Induction Motor

To get the desired response of the sensor less Vector controlled Induction Motor (SVC-IM) by the experimental setup, the controller implementation for the generation of the PWM signals is the key role. It is possible with the rapid growth of electronic industry such as high speed digital signal processors (DSPs) with micro controllers available in the present market. In the past DSP technologies were used to realize the several SVC-IM schemes, i.e. KF, PI, GA and PSO respectively. However, it creates issues related to the time delay and execution of the PWM signals, etc., as a results system becomes complex. Therefore a new approach is implemented to overcome the issues related to the execution time, namely Field Programmable Gate Array (FPGA) processors are suggested in the present market. Moreover the programming is done using very high speed hardware descriptive language (VHDL).