High-speed Digital Communication Systems Research Articles

Eye Surgical Equipment Sensor Board Testing Kit

The Eye Surgical Equipment Sensor Board Testing Kit utilizes Microcontroller and Raspberry Pi to diagnose PCBs, focusing on detecting Eye Surgical Sensor Board defects impacting signal integrity. With Microcontroller’s advanced features like high-speed ADCs and flexible GPIOs, it generates and processes signals accurately. Raspberry Pi enables real-time visualization of test results. This portable and cost-effective solution is suitable for industrial applications, empowering engineers and technicians to efficiently address Eye Surgical Sensor Board defects. By leveraging the computational power of both platforms, it offers a scalable approach to Sensor Board testing, enhancing reliability and performance in high-speed digital communication systems.

All optical modulation in vertically coupled indium tin oxide ring resonator employing epsilon near zero state

We present an innovative approach to achieve all-optical modulation within an ITO-based vertically coupled ring resonator. This method leverages the material's enhanced nonlinear response in the near-infrared wavelengths, particularly within the epsilon-near-zero (ENZ) state. To enhance the interaction between light and the material while minimizing scattering losses, our approach employs an ITO-based vertically connected ring resonator. The vertical arrangement eliminates the need for etching fine gaps to separate the ring and bus waveguide. The novel waveguide design addresses the necessity of high sensitivity, non-linear effects and compact size opening the possibilities for all-optical signal processing. This unique resonator structure effectively facilitates the coupling of a high-intensity pump wavelength into the ITO-based micro-ring resonator. Consequently, this optical pumping induces electron heating within the ITO material, leading to a significant increase in its nonlinear optical properties. This, in turn, results in a noteworthy alteration of ITO's refractive index, specifically in the unity order, thereby modifying the complex effective index of the optical beam propagating at 1550 nm. Our experimental findings demonstrate an impressive extinction ratio of 18 dB for a 30 µm long device, which highlights the efficiency of our approach in achieving all-optical modulation through the optical pumping of an ITO-based vertically coupled ring resonator. The proposed all-optical modulator has outperformed as compared to conventional waveguide-based modulators in terms of extinction ratio and footprint. This novel technique holds immense potential for advancing high-speed data communication systems in the future. As the demand for advanced processing capabilities, such as artificial intelligence, continues to grow, all-optical modulation emerges as a groundbreaking technology poised to revolutionize the next generation of computing and communication systems.

Nano-ITLA Based on Thermo-Optically Tuned Multi-Channel Interference Widely Tunable Laser

A tunable light source with narrow linewidth, small size and low power consumption is necessary for high-speed digital coherent communication system. We have developed a monolithically integrated narrow linewidth widely tunable laser—multi-channel interference (MCI) laser, which realizes a quasi-continuous tuning range covering the C++ band. By packaging the laser chip, wavelength locker and thermoelectric cooler (TEC) into a transmitter optical subassembly (TOSA) box and designing a compact print circuit board (PCB), a nano-integrable tunable laser assembly (Nano-ITLA) based on the thermo-optically tuned MCI laser is demonstrated for the first time. The Nano-ITLA is 25.0 mm (L) × 15.6 mm (W) × 6.5 mm (H), and realizes 120 International Telecommunication Union (ITU)-grid switching over 48 nm and less than 3 W total power consumption. The side-mode suppression ratios (SMSRs) are higher than 46 dB, the fiber coupled output powers are greater than 16 dBm, and the Lorentzian linewidths are less than 150 kHz. High precision wavelength locking and temperature control system make the output frequency deviation of all channels from the ITU-grid less than ± 0.5 GHz and the wavelength drift less than ± 1 pm. The output power can be accurately controlled and stabilized at ± 0.1 dB through a closed-loop feedback. The no-light shutdown function realizes an extinction ratio higher than 40 dB during wavelength switching. The Nano-ITLA demonstrates excellent application potential in the coherent optical communications.

A 3D Modulation Scheme for High-speed Baseband Digital Communication System

To improve the transmission rate of wireless communications, the communication frequency band will gradually go higher, and the use of millimeter wave and terahertz will become mainstream in the future. However, the signal attenuation in high bands is considerable, which prevents the achievement of long-distance transmissions. In this paper, we propose a 3D modulation scheme that is especially suitable for high-speed baseband digital communication systems. The proposed scheme is simulated and tested in an experiment. With the same order of modulation, the 3D modulation shows a significant decrement in bit error rate and enables a longer transmission distance.

Emerging light-emitting diodes for next-generation data communications

The continuing development of consumer electronics, mobile communications and advanced computing technologies has led to a rapid growth in data traffic, creating challenges for the communications industry. Light-emitting diode (LED)-based communication links are of potential use in both free space and optical interconnect applications, and LEDs based on emerging semiconductor materials, which can offer tunable optoelectronics properties and solution-processable manufacturing, are of particular interest in the development of next-generation data communications. Here we review the development of emerging LED materials—organic semiconductors, colloidal quantum dots and metal halide perovskites—for use in optical communications. We examine efforts to improve the modulation performance and device efficiency of these LEDs, and consider potential applications in on-chip interconnects and light fidelity (Li-Fi). We also explore the challenges that exist in developing practical high-speed LED-based data communication systems. This Review examines the development of emerging semiconductor materials—organic semiconductors, colloidal quantum dots and metal halide perovskites—for light-emitting diodes, considering efforts to improve modulation performance and device efficiency, as well as potential applications in on-chip interconnects and light fidelity (Li-Fi).

A 4GS/s 8‐bit time‐interleaved SAR ADC with an energy‐efficient architecture in 130 nm CMOS

AbstractThis paper presents the design, implementation, and measurements of a 4 GS/s, 8‐bit resolution, time‐interleaved (TI) analog‐to‐digital converter (ADC) comprised of 32 asynchronous successive approximation register (SAR) ADCs. The chip is fabricated in a 130 nm CMOS process. This prototype achieves the highest sampling rate and the best efficiency for a SAR TI‐ADC in the process used. An energy‐efficient hierarchical T&H architecture, ranked in a 4 × 8 structure, has been used to interleave the aforementioned high number of SAR ADCs avoiding the power hungry buffers typically used in the input signal path and/or T&H outputs. The sampling architecture includes programmable delay cells with up to 104 fs resolution to calibrate sampling time errors. Additionally, the input matching network uses an on‐chip inductance to mitigate the impact of the packaging on the analog bandwidth. An efficient SAR ADC implementation is achieved by an optimized comparator design, which allows for both, noise and asynchronous clock control, and includes background DC offset calibration. The test chip is the core of a measurement platform dedicated to the evaluation of mismatch calibration techniques for ADCs used in high speed digital communication systems. To enable this application, a 32Gb/s low‐voltage differential signaling interface is included to transmit the samples off‐chip without any decimation. The TI‐ADC achieves a peak 7.09 effective number of bits (ENOB) (5.47ENOB at Nyquist) and 1.3 GHz input bandwidth with a power consumption of 93 mW at 1.2 V. Each SAR ADC channel achieves a Walden figure of merit (FOM) of 123fJ/conv‐step and owing to the efficient interleaved architecture the full TI‐ADC achieves a peak FOM of 171fJ/conv‐step (526fJ/conv‐step at Nyquist).

Fast and Accurate Decomposition of Deterministic Jitter Components in High-Speed Links

In a high-speed digital communication system, jitter performance plays a crucial role in bit-error rate. It is important to accurately derive each type of jitter as well as total jitter and to identify root causes of jitter by jitter decomposition as a key tool. In this paper, we extend our previously reported algorithm to decompose duty cycle distortion as well as other deterministic jitter components including periodic jitter (PJ), intersymbol interference (ISI), and random jitter (RJ), and describe more detail of this algorithm with extensively simulation and measurements to verify the algorithm. The proposed ISI model only requires the time invariant condition, which is true for almost all systems, while the traditional ISI model is valid only with linear time invariant assumption. Compared to the conventional methods, the proposed jitter decomposition method is able to obtain estimated individual jitter component values with good accuracy by using fewer samples of total jitter data. The efficiency and accuracy of the proposed method were demonstrated by simulation and hardware experiments.

A Low-Cost Comparator-Based Method for Accurate Decomposition of Deterministic Jitter in High-Speed Links

Jitter decomposition is a key tool to identify root causes of jitters in a high-speed digital communication system. It is a huge challenge in balancing the test cost and precision for conventional decomposition methods implemented in instruments where the time interval error (TIE) data are necessary. In this paper, we propose a deterministic jitter decomposition method using Boolean output from a network of simple low-cost comparators to identify the deviation of current sampling position from the ideal sampling position instead of TIE data. The new method simultaneously separates intersymbol interference (ISI), periodic jitter (PJ), and duty cycle distortion (DCD). Simulation and measurement results demonstrate that the proposed method can estimate the ISI, PJ, and DCD with sufficient accuracy using significantly fewer data samples than the state-of-the-art instrument test, and thus, reduce test cost greatly. Furthermore, the comparators have extremely relaxed design requirements, offering potential for possible on-chip implementation for built-in self-test or background test.

Performance Analysis of OFDMA and SC-FDMA

The main challenge in any high-speed digital communication system is how to maximize the data rate with minimizing the bit error rate. Several techniques have been developed to achieve this point. Some of these techniques are orthogonal frequency division multiplexing (OFDM), single-carrier frequency domain equalization (SC-FDE), orthogonal frequency division multiple access (OFDMA), and single-carrier frequency division multiple access (SC-FDMA). These four techniques are described briefly in this paper. Also, the paper measures the performances of OFDMA and SC-FDMA systems over international telecommunication union (ITU) vehicular-A channel using minimum mean square error (MMSE) equalization. Simulation results show that the performances with interleaved mapping outperform that with localized mapping. Also, the performances with quadrature phase shift keying(QPSK) are better than that with 16-ary quadrature amplitude modulation (16QAM). In addition, the performance of SC-FDMA is better than that of OFDMA, when QPSK is used, but the latter is little bit better than that of SC-FDMA when 16QAM is used

Performance analysis of OFDMA and SC-FDMA

The main challenge in any high-speed digital communication system is how to maximize the data rate with minimizing the bit error rate. Several techniques have been developed to achieve this point. Some of these techniques are orthogonal frequency division multiplexing (OFDM), single-carrier frequency domain equalization (SC-FDE), orthogonal frequency division multiple access (OFDMA), and single-carrier frequency division multiple access (SC-FDMA). These four techniques are described briefly in this paper. Also, the paper measures the performances of OFDMA and SC-FDMA systems over international telecommunication union (ITU) vehicular-A channel using minimum mean square error (MMSE) equalization. Simulation results show that the performances with interleaved mapping outperform that with localized mapping. Also, the performances with quadrature phase shift keying (QPSK) are better than that with 16-ary quadrature amplitude modulation (16QAM). In addition, the performance of SC-FDMA is better than that of OFDMA, when QPSK is used, but the latter is little bit better than that of SC-FDMA when 16QAM is used.

Study of Slotted Array Waveguide with High Peak Gain Antenna for Data Communication

Objectives: This article manifests a study of high peak gain of a slotted array waveguide antenna. At first, two similar slot lengths 2-elements shunt slotted array antenna structures (i.e. Case-1) and two dissimilar slot lengths 2-elements shunt slotted array antenna structures (i.e. Case-2) are designed one by one. Methods/Statistical Analysis: The Multiple Cavity Modeling Technique (MCMT) has been applied in both cases of structural antennas. The scattering parameters (i.e. |S11| and |S21|) data have been computed for both cases of 2-element shunt slotted array antenna. The MCMT |S11| and |S21| data graphs have been compared with Ansoft High Frequency Structure Simulator (HFSS) simulated data graphs. Comparison results signify that a slight difference between computed and simulated data. Findings: Subsequently, the HFSS simulated gains total of the both cases of design structures antenna are obtained. The outcome found in 2-element shunt slotted array with similar slot length gains higher total rather than dissimilar slot length 2-element shunt slotted array antenna. In order to achieve further increases in gain a 2-elements lotted array antenna up to optimal point was extended up to seven slots. Analysis was done to compare the results with theoretical and simulated HFSS results. Application /Improvement: The antenna finds its application in high speed data communication system in the area of aircraft.

BER Performance of QAM and QPSK Modulation Technique for DCT Based Channel Estimation of STBC MIMO OFDM

Consumer demand for high speed data communication system is increasing day by day. However the major challenges for wireless communication system are Inter Symbol Interference (ISI) and Inter Carrier Interference (ICI) that occur during data transmission. This interference will distort signal and increase error rate in the system. Combination of Orthogonal Frequency Division Multiplexing (OFDM) and Multiple Input Multiple Output (MIMO) give a reliable high data rate. Discrete Cosine Transform (DCT)-based channel estimation is used in STBC MIMO-OFDM and simulated using MATLAB software. The system performance is compared with multiple antenna configuration and different modulation technique. Multiple antenna configurations that involve during simulation are 2x2, 4x4 and 6x6 while modulation techniques are Quadrature Amplitude Modulation (QAM) and Quadrature Phase Shift Keying (QPSK). This simulation will prove that the higher number of transmit and receive antenna, the lower BER for the system.

High-Performance and High-Data-Rate Quasi-Coaxial LTCC Vertical Interconnect Transitions for Multichip Modules and System-on-Package Applications

A new design of stripline transition structures and flip-chip interconnects for high-speed digital communication systems implemented in low-temperature cofired ceramic (LTCC) substrates is presented. Simplified fabrication, suitability for LTCC machining, suitability for integration with other components, and connection to integrated stripline or microstrip interconnects for LTCC multichip modules and system on package make this approach well suited for miniaturized, advanced broadband, and highly integrated multichip ceramic modules. The transition provides excellent signal integrity at high-speed digital data rates up to 28 Gbits/s. Full-wave simulations and experimental results demonstrate a cost-effective solution for a wide frequency range from dc to 30 GHz and beyond. Signal integrity and high-speed digital data rate performances are verified through eye diagram and time-domain reflectometry and time-domain transmissometry measurements over a 10-cm long stripline.

Energy Efficient Programmable MIMO Decoder Accelerator Chip in 65-nm CMOS

This paper presents an energy efficient programmable hardware accelerator that targets multiple-input-multiple-output (MIMO) decoding tasks of orthogonal frequency-division multiplexing (OFDM) systems. The work is motivated by the adoption of MIMO and OFDM by almost all existing and emerging high-speed wireless data communication systems. The accelerator was fabricated in 65-nm CMOS technology and occupies a core area of 2.48 mm 2 . It delivers full programmability across different wireless standards (i.e., WiFi, 3G-long term evolution, and WiMax) as well as different MIMO decoding algorithms (i.e., minimum mean square error, singular value decomposition, and maximum likelihood) with extreme energy efficiency. The energy efficiency of our MIMO accelerator chip was compared against dedicated application specific integrated circuits for 4 × 4 QR decomposition, 4 × 4 singular value decomposition, and 2 × 2 minimum mean square error decoding. Despite the programmable nature of our design, it delivered energy efficiencies that were 18% to 28% better than the dedicated solutions reported in the literature. This paper presents the VLSI implementation of the architecture discussed in [14]-[16]. It discusses the implementation decisions and tradeoffs used to ensure minimum overall energy consumption of the resulting accelerator chip without sacrificing programmability. Given its programmability and extreme energy efficiency, the accelerator is an ideal solution for today's smart phones that implement multiple MIMO-OFDM waveforms on the same platform.

PERFORMANCE ANALYSIS OF DIGITAL BEAMFORMING ALGORITHMS

Interference reduction is needed for being able to effectively communicate with mobile users. One method that can be used as a solution to reduce interference is using smart antenna technology. Along with interference reduction there is increase in capacity and coverage. Adaptive beam forming techniques forms a narrow beam and directs it towards desired users and thereby forms nulls in interference directions This improves signal to noise ratio. The study documented in this paper shows the performance of variants of the Least Mean Square (LMS) Algorithm based approaches, in the realm of beam formation, used earlier in adaptive filtering, aiming at reduction in complexity, without considerable degradation in performance. The proposed algorithms namely Signum- Error Least Mean Square Algorithm along with LMS Algorithm are tested for computational complexity in weight vector updating and observed that the ones proposed perform better than the conventional Least Mean Square algorithm with respect to reduced complexity in beam formation, making them suitable for high speed digital communication systems. This paper will analyze Least Mean square algorithm and Sample Matrix Inverse algorithm for the performance. The consequence will demonstrate the Least Mean Square as a Solution to jammer cancellation when compared to Sample Matrix Inverse.

Proposed Inductor Design for High Speed Digital Communication Systems through Divergence Analysis of Self Inductance and Variability in Permeability Values of Unaltered Human Hair

The Dielectric Losses associated with inductors play more considerable role at higher frequencies. Parasitic capacity determines the magnitude of these losses. The permeability is one of the factors that affect self-inductance of a solenoid directly. Change of medium from free space to any other element like iron or plastic may change the behavior of solenoid. Human hair is primarily composed of keratin. Keratin is considered as a good insulator. However an electric charge gained by the hairs due to friction and this phenomenon is called tribo-electric effect. It gives hair an ability to become charged with static electricity. The scenario tested with coils is wrapped around human hairs and the air between them as a medium. It is hypothesized that replacement of iron by human hair will vary the self-induction. The reference or test validation platform for the experiment was an air and iron core inductor. The reason behind this choice was its wide use in various applications like power supplies, metal detectors, car ignition coils and even in high speed digital systems. The observed values of induced e.m.f for the scenario are used to analyze the deviation in self-Inductance phenomenon. The theoretical model for the air and iron core solenoid is also compared with the resulting values to calculate and reaffirm the permeability values of the human hair especially for South Asian ethnic region.

Adaptive Blind Equalization of QAM Transmitted Constellations across Linear Band-Limited Channel

ISI (Intersymbol Interference) severely degrades the performance of high speed digital communication systems. A popular technique for countering ISI is Adaptive Equalization. Blind/Unsupervized equalization is one class of adaptive equalization where initial training of equalizer’s weights is not feasible. Godard’s Constant Modulus Algorithm (CMA) was the very first blind equalization algorithm that could be applied for two dimensional communication systems. It requires the transmitted signal’s statistics to perform equalization. Picchi & Prati modified the standard decision-directed algorithm and proposed a new algorithm by the name Stop-and-Go. Wei Rao by simply converting the equalizer’s output proposed a modified version of the CMA. This paper compares the performance of blind equalization algorithms: CMA, Stop-and-Go decisiondirected algorithm and Wei Rao’s modified constant modulus algorithm for 16 and 64-QAM constellations transmitted across a linear band-limited channel. Simulation results indicate impulse response of the cascade of transmission channel and equalizer (after convergence) is similar to that of ideal transmission channel‘s impulse response. The results also show that stop-and-go outperforms the rest in terms of convergence rate and MSE.

Enhanced passive equaliser using open‐stub structure

An open-stub compensation technique is proposed for passive equalisers used in high-speed digital communication systems. By simply lumping an open stub to the conventional RL-type passive equaliser, the frequency-dependent channel loss from the long transmission path can be compensated, the frequency response of the channel becomes more flat and the bandwidth is wider. On comparing the proposed passive equaliser with typical RL passive equalisers, the simulation results show that the proposed technique can achieve an improvement by 1 GHz in the flat region of S 21 on a 60 cm-long differential pair. Thus, the proposed technique successfully demonstrates an improvement in electrical performance of about 57.4% in the time domain.

Mach-Zehnder: A Review of Bias Control Techniques for Mach-Zehnder Modulators in Photonic Analog Links

The Mach-Zehnder modulator (MZM) has been widely used for broadband photonic analog links and high-speed digital optical fiber communication systems because it possesses large modulation bandwidth, low driving voltage, and low chirp. The MZM is a very important optical modulator for photonic applications. In an MZM, the input light is split into two paths, each of which is modulated by an electrical signal. Then the two arms are combined to generate an intensity-modulated light or a phase-modulated light at the output of the MZM. An MZM can be made of lithium niobate (LiNbO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ), gallium arsenide (GaAs), or indium phosphide (InP), materials that exhibit some anisotropy in their dielectric properties. Theoretically, the relation of output optical field and driving voltage is a cosine function, i.e., nonlinear transfer function. For RF photonics, the MZM has typically two applications: optical harmonic generation for optical frequency multiplication and optical subcarrier modulation for optical signal modulation. For optical frequency multiplication, high transfer-function nonlinearity is preferred. In contrast, high transfer-function linearity is preferred for optical subcarrier modulation. It is well known that a cosine transfer function can present high or low nonlinearity dependent on operation voltage. Specifically, bias voltages determine the degree of nonlinearity or linearity of the MZM transfer function. For optical frequency multiplication such as millimeter-wave generation, the MZM should be biased at some specific bias points, such as minimum transmission, maximum transmission, and quadrature bias points, to enhance nonlinearity [1]?[2]. For optical subcarrier modulation, biasing an MZM in its linear region such as quadrature bias points allows transmitting broadband RF signals with multioctave bandwidth and improves spurious free dynamic range (SFDR). Therefore, care must be taken to maintain and control the MZM bias point for a specific application.

45nm CMOS 공정기술에 최적화된 저전압용 이득-부스팅 증폭기 기반의 1.1V 12b 100MS/s 0.43㎟ ADC

본 논문에서는 주로 고속 디지털 통신시스템 응용을 위해 고해상도, 저전력 및 소면적을 동시에 만족하는 45nm CMOS 공정으로 제작된 4단 파이프라인 구조의 12비트 100MS/s ADC를 제안한다. 입력단 SHA 회로에는 높은 입력 주파수를 가진 신호가 인가되어도 12비트 이상의 정확도로 샘플링할 수 있도록 게이트-부트스트래핑 회로가 사용된다. 입력단 SHA 및 MDAC 증폭기는 요구되는 DC 이득 및 높은 신호스윙을 얻기 위해 이득-부스팅 구조의 2단 증폭기를 사용하며, 넓은 대역폭과 안정적인 신호정착을 위해 캐스코드 및 Miller 주파수 보상기법을 선택적으로 적용하였다. 채널길이 변조현상 및 전원전압 변화에 의한 전류 부정합을 최소화하기 위하여 캐스코드 전류 반복기를 사용하며, 소자의 부정합을 최소화하기 위하여 전류 반복기와 증폭기의 단위 넓이를 통일하여 소자를 레이아웃 하였다. 또한, 제안하는 ADC에는 전원전압 및 온도 변화에 덜 민감한 저전력 기준 전류 및 전압 발생기를 온-칩으로 집적하는 동시에 외부에서도 인가할 수 있도록 하여 다양한 시스템에 응용이 가능하도록 하였다. 제안하는 시제품 ADC는 45nm CMOS 공정으로 제작되었으며 측정된 DNL 및 INL은 각각 최대 0.88LSB, 1.46LSB의 값을 가지며, 동적성능은 100MS/s의 동작속도에서 각각 최대 61.0dB의 SNDR과 74.9dB의 SFDR을 보여준다. 시제품 ADC의 면적은 0.43mm2 이며 전력소모는 1.1V 전원전압 및 100MS/s 동작속도에서 29.8mW이다.