High-speed ATM Switching Research Articles

640-Gb/s high-speed ATM switching system based on 0.25-μm CMOS, MCM-C, and optical WDM interconnection

A 640-Gb/s high-speed ATM switching system that is based on the technologies of advanced MCM-C, 0.25-/spl mu/m CMOS, and optical wavelength-division-multiplexing (WDM) interconnection is fabricated for future broadband backbone networks. A 40-layer, 160/spl times/114 mm ceramic MCM forms the basic ATM switch module with 80-Gb/s throughput. It consists of 8 advanced 0.25-/spl mu/m CMOS LSIs and 32 I/O bipolar LSIs. The MCM has a 7-layer high-speed signal line structure having 50-/spl Omega/ strip lines, high-speed signal lines, and 33 power supply layers formed using 50-/spl mu/m thick ceramic layers to achieve high capacity. A uniquely structured closed-loop-type liquid cooling system for the MCM is used to cope with its high power dissipation of 230 W. A three-stage ATM switch is made using the optical WDM interconnection between high-performance MCMs. For WDM interconnection, newly developed compact 10-Gb/s, 8-WDM optical transmitter and receiver modules are used. These modules are each only 80/spl times/120/spl times/20 mm and dissipate 9.65 W and 22.5 W, respectively. They have a special chassis for cooling, which contains high-performance heat-conductive plates and micro-fans. An optical WDM router based on an arrayed waveguide router is used for mesh interconnection of boards. The optical WDM interconnect has 640-Gb/s throughput and simple interconnection.

Performance evaluation of a high-speed ATM switch with multiple common memories

We consider a common-memory (CM) type N /spl times/ N ATM switch, where CM block consists of K (K /spl ges/ N) separated submemories. We propose an address assignment algorithm to avoid input/output contentions so that we can have the read/write speed of submemories as low as the interface (input/output) port speed. Taking a replication-at-sending approach to multicast, we pursue memory efficiency and maximum throughput. We develop an analytical model to evaluate the system in terms of cell loss ratio and average delay time. In the analysis, we take into account two loss factors causing losses of incoming cells: (1) the failure of scheduling to avoid the input/output contentions and (2) overflow in the CM block. The first factor is dominating and can be significantly reduced by increasing K. From our analytical results compared with simulations, it is observed that we can take K /spl ap/ 3N as a guide of system design.

Burst-based scheduling algorithms for non-blocking ATM switches with multiple input queues

This letter quantitatively evaluates two alternative approaches to the scheduling of traffic streams in a high-speed ATM switch with multiple input queues. Specifically, we compare a previously proposed algorithm, called parallel iterative matching (PIM)-which is a cell-based scheduling algorithm-with our newly proposed algorithm-which is a burst-based variation of the PIM scheduling algorithm. Extensive simulation results demonstrate that burst-based PIM scheduling outperforms cell-based PIM scheduling under a variety of realistic parameters.

On the speedup required for combined input- and output-queued switching

Architectures based on a non-blocking fabric, such as a crosspoint switch, are attractive for use in high-speed LAN switches, IP routers, and ATM switches. When operating at the highest speed, memory bandwidth limitations dictate that queues be placed at the input of the switch. But it is well known that input-queueing can lead to low throughput, and does not allow the control of latency through the switch. This is in contrast to output-queueing which maximizes throughput and permits the accurate control of packet latency through scheduling. We ask the question: Can a switch with combined input and output queueing be designed to behave identically to an output-queued switch? In this paper, we prove that if the switch uses virtual output queueing and has an internal speedup of just four, it is possible for it to behave identically to an output-queued switch, regardless of the nature of the arriving traffic. Our proof is based on a novel scheduling algorithm, called Most Urgent Cell First. We find that with a speedup of four the most urgent cell first algorithm (or MUCFA) enables perfect emulation of a FIFO output-queued switch, i.e. one in which packets depart in the same order that they arrived. We extend this result to show that with a small modification, the MUCFA algorithm enables perfect emulation of a variety of output scheduling policies, including strict priorities and weighted fair-queueing. This result makes possible switches that perform as if they were output-queued, yet use memories that run more slowly.

An efficient packet service algorithm for high-speed ATM switches

The unprecedent development of the World Wide Web, and the emerging of new types of applications such as video-on-demand and teleconferencing put an increasing pressure on the communication infrastructure. One of the main components that directly determine the communication bandwidth and the quality of services that are provided are the communication switches. In this paper, we propose a new scheduling algorithm for servicing the output sessions of a high-speed ATM switch that is both accurate and efficient. To each session we associate a weight w that represents the share of the communication bandwidth it should receive. To characterize the allocation accuracy we give bounds for the difference (called lag) between the number of time slots that each session should receive and the number of time slots it actually receives. Specifically, we show that in the particular case in which the aggregate weight W over all sessions is a power of two, the lag of a session with weight w is bounded by O( ones( w)), where ones( w) represents the number of ones in the binary representation of w. In the general case in which the aggregate weight has an arbitrary value, we show that the session's lag is bounded by O(log w). The selection of the session to be serviced during the next time slot takes O(log log W). We also propose a simple hardware implementation that reduces the selection time complexity to O(1). Finally, we discuss the application of our algorithm in the context of both work-conserving and non-work-conserving disciplines.

An integrated call admission and buffer management scheme for LAN interconnection over a shared-memory ATM switch

We consider the problem of interconnecting low speed LANs over a high-speed shared-memory ATM switch. A bottleneck is formed when more than one source originate traffic to the same destination LAN. In this case, a congestion may be created at the output gateway (destination LAN interface) and the required services are interrupted. In this paper we propose a new integrated scheme for call admission (CAC) and buffer management. The objective of the scheme is to prevent the congestion at the destination LANs, as well as within the ATM switch, while minimizing connection rejection rates (maximizing the utilization of the ATM switch). The scheme uses two types of parameters: first, the connection parameters which are estimated at the network interface unit and specified during connection set-up, and second, the actual traffic characteristics and buffer requirements. Therefore, the proposed scheme combines both parameter-based and measurement-based approaches to the problems of call admission and congestion control. The proposed scheme is shown not to require intensive computations and can be implemented in real time in a high-speed ATM switch. A simulation model for the system is developed from which the performance of our integrated CAC and buffer management scheme is evaluated. It is shown that the application of our CAC criteria maintains cell/packet dropping to within the same order of magnitude. It is also shown that using virtual buffer allocation, in conjunction with our CAC criteria, results in almost no cell/packet dropping.

Scalable architectures for integrated traffic shaping and link scheduling in high-speed ATM switches

Emerging broad-band switches must accommodate the diverse traffic parameters and quality-of-service requirements of voice, data, and video applications. End-to-end performance guarantees depend on connections complying with traffic contracts as their cells travel through the network. This paper presents a leaky-bucket shaper architecture that scales to a large number of connections with diverse burstiness and bandwidth parameters. In contrast to existing designs, the proposed architecture arbitrates fairly between connections with conforming cells by carefully integrating leaky-bucket traffic shaping with rate-based scheduling algorithms. Through a careful combination of per-connection queueing and approximate sorting, the shaper performs a small, bounded number of operations in response to each arrival and departure, independent of the number of connections and cells. When the shaper must handle a wide range of rate parameters, a hierarchical arbitration scheme can reduce the implementation overheads and further limit interference between competing connections. Through simulation experiments, we demonstrate that the architecture limits cell-shaping delay and traffic distortions, even in periods of heavy congestion. The efficient combination of traffic shaping and link scheduling results in an effective architecture for managing buffer and bandwidth resources in large, high-speed ATM switches.

A 2.5 Gb/s ATM switch chip set

The design and implementation of two application specific integrated circuits used to build an ATM switch are described. The chip set is composed of the CMC which is an input/output processor of ATM cells implemented on a BICMOS 0.7 /spl mu/m technology and the ICM, a 0.7 /spl mu/m CMOS IC, that performs cell switching at 68 MHz. The ATM switch exploits parallelism and segmentation to perform 2.5 Gb/s switching per input/output. The main advantage of the high-speed link rates in the range of Gb/s, is the exploitation of statistical gain with bursty high peak rate sources. Another feature of the high speed ATM switches is that the number of interface devices and stages is reduced on an ATM network. To demonstrate the usefulness of the switch, an evaluation of the network efficiency improvement by using statistical gain is presented in the paper.

Self-firing cell scheduler for input queueing ATMswitches

The authors propose a simple cell scheduler for input queueing ATM switches. The proposed self-firing cell scheduler consists of N2 processing elements connected by a two dimensional torus network, where each processing element can determine the diagonal by itself in a distributed manner. It allows a simple implementation for high speed ATM switches.

320 Gb/s high-speed ATM switching system hardware technologies based on copper-polyimide MCM : NAOKI YAMANAKA et al. IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B, 181(1), 83 (February 1995)

320 Gb/s high-speed ATM switching system hardware technologies based on copper-polyimide MCM : NAOKI YAMANAKA et al. IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B, 181(1), 83 (February 1995)

Heat-pipe cooling for high-speed ATM switching MCMs

Heat-pipe cooling for high-speed ATM switching MCMs

80 Gbit/s ATM switching module based oncopper-polyimide MCM

An 80 Gbit/s high-speed multichip ATM switching module for broadband ISDN is described. The module employs a copper-polyimide MCM with four-layer copper-polyimide signal transmission layers and 15-layer ceramic power supply layers. All MCMs are interconnected by 98-highway flexible printed circuit connectors. Four Si-bipolar VLSIs are mounted on an MCM using the 150 µm, very-thin-pitch, outer lead TAB technique. In addition, a high-performance heat-pipe cooling technique is adopted. The switching module handles ATM cell rates of up to 80 Gbit/s and so will support the future B-ISDN.

320 Gb/s high-speed ATM switching system hardware technologies based on copper-polyimide MCM

This paper describes a 320 Gb/s high-speed multichip ATM switching system for broadband ISDN. This system employs a copper-polyimide MCM with 4-layer copper-polyimide signal transmission layers and 15-layer ceramic power supply layers. The system uses 64 MCMs that are interconnected by 98-highway flexible printed circuit connector. Si-bipolar VLSI's are mounted on MCM's using the 150 /spl mu/m very-thin pitch outer lead TAB technique. In addition, a high-performance heat-pipe air cooling technique is adopted. The system switches ATM cells up to 320 Gb/s throughput, which is applicable for future B-ISDN. >

An input buffer-type ATM switching system using schedule comparison

An input buffer-type, high-capacity ATM switching system using schedule comparison is proposed for a high-speed ATM switching system whose internal link speed is equal to trunk speed. Its throughput, delay, and loss characteristics are evaluated. The schedule of the input buffer to send cells and that of the output to receive cells are compared to decide the timing to send a cell so that there exists only one cell bound for the same output line. The maximum throughput (outgoing trunk efficiency) is more than 0.9, and the mean delay is less than 10 cell times. Moreover, if a doubled transfer network is used, higher throughput can be achieved and the delay characteristic is almost equal to that with an ideal output buffer type. A comparison of the proposed scheme with the output buffer-type system under the same cell loss probability 10−5 reveals that the delay is almost the same and the required buffer size is one-third. This characteristic holds even if the system size is extended to 4096 lines; hence, a super high-capacity, high-speed switching system can be configured with the proposed system.