High-sensitivity CMOS Image Sensor Research Articles

High-definition and high-sensitivity CMOS image sensor with all-pixel image plane phase-difference detection autofocus

In this paper, we describe an overview of autofocus (AF) technology for digital still cameras, video camcorders, and smartphones. Subsequently, we propose a CMOS image sensor (CIS) with all-pixel image plane phase-difference detection AF (PDAF) and describe a device structure and an optical design for fast and high-quality AF and low-noise imaging. To perform both PDAF and imaging function in all pixels, an individual pixel is composed of two horizontally displaced sub-photodiodes (PDs) and one microlens (ML). In particular, we describe PD and pixel isolation technology for high-definition, high-sensitivity, and low-noise PDAF-CIS with about front-side-illuminated (FSI) 6.4-µm-size pixel and back-side-illuminated (BSI) 1.X µm-size pixels.

A Double-Layered Microlens for High-Sensitivity CMOS Image Sensors

Pixel sizes of CMOS image sensors continue to decrease to below 1.0 μm for high-resolution applications. However, the sensitivity of pixels is declining and the crosstalk is increasing as the size of the pixel pitch is reduced. In this paper, a double-layered microlens for a high-sensitivity CMOS image sensor is suggested. The double-layered microlens is formed by four microlenses on the top layer and one microlens on the bottom layer. To investigate the performance of the suggested structure, we used three-dimensional optical simulation to compare the absorptivity of backside-illuminated 0.9 μm, 1.0 μm, and 1.4 μm pixels with the typical microlens and the double-layered microlens. The finite-difference time-domain (FDTD) method was used for a numerical analysis on the optical characteristics. Having compared the typical pixel with the suggested pixel, the double-layered microlens shows excellent crosstalk performance at an oblique incident light for 0.9 μm, 1.0 μm, and 1.4 μm pixels.

A Low Dark Leakage Current High-Sensitivity CMOS Image Sensor With STI-Less Shared Pixel Design

A CMOS image sensor with a low dark current and high sensitivity is developed with shallow trench isolation (STI) less shared pixel. By sharing in-pixel transistors, such as the reset transistor, select transistor, and source follower amplifier, each pixel achieves a high fill factor of 43% and a high sensitivity of 144.6 ke <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> /lx · s. In addition, compared with a conventional image sensor which has the STI structure in the pixel for isolation, the developed image sensor achieves a relatively low dark current of 104.5 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> /s/pixel (median), corresponding to a current density J <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dark</sub> of approximately 30 pA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at 60 °C. This is a low value and the consequence of not using STI as pixel isolation. Both types of pixels, namely the conventional and the proposed active pixel sensor have the same pixel size of 7.5 × 7.5 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and are fabricated by the same process. The developed imager with STI-less shared pixel obtains sufficiently good responses at 400 to 900 nm, and, particularly, a peak QE of 68% at 600 nm. This is suitable for scientific applications.

A 200-$\mu$V/e$^{-}$ CMOS Image Sensor With 100-ke$^{-}$ Full Well Capacity

A high-sensitivity CMOS image sensor keeping a high full-well capacity has been developed by introducing a new pixel having a small floating diffusion (FD) capacitance connected to a lateral overflow integration capacitor (LOFIC) through a MOS switch. The conceptual advantage of the small FD approach over conventional column amplifier approaches is compared and demonstrated. To ensure both the high sensitivity and the high full-well capacity, the low-light and the bright-light signals (S1 and S2) are output and reproduced without a visible SNR degradation at the S1/S2 switching point. As the most critical problem, the increase of the conversion gain variation in this approach is suppressed by applying a self-aligned offset structure to the small FD. A 1/4-in VGA format CMOS image sensor fabricated through 0.18-mum 2P3M process achieves 2.2-e- rms noise floor with 200-muV/e- conversion gain and 100-ke- full-well capacity.

A high-sensitivity CMOS image sensor with gain-adaptive column amplifiers

A high-sensitivity CMOS image sensor using gain-adaptive column amplifiers is presented and tested. The use of high gain for the column amplifier reduces input-referred random noise, and when coupled with a column-based digital noise cancellation technique, also reduces fixed pattern noise. An experimental application of the circuit using 0.25-/spl mu/m CMOS technology with pinned photodiodes gave an rms random noise of 263 /spl mu/V and an rms fixed pattern noise of 50 /spl mu/V.