High Resolution Digital Pulse-width Modulator Research Articles

Adaptive Self-Tuned Controller IC for Resonant-Based Wireless Power Transfer Transmitters

This article introduces an adaptive self-tuned controller IC for resonant wireless power transfer (RWPT) transmitters. The controller IC comprises an on-the-fly very-high-frequency tracking hardware with high resolution and an independent high-resolution digital pulsewidth modulator (PWM)-based (HR-DPWM) current programmed control. These facilitate precise frequency generation as well as adaptive tuning of the reactive components in the matching network, which translate into tight current/power regulation capabilities while retaining optimized power transfer conditions on the transmitting side. The controller IC enables to effectively disengage the power-delivery capabilities from the variations of the resonators, electrical circuits, and wireless medium. The controller core is based on a fully synthesizable digital architecture that has been realized through HDL tools, and several key building blocks have been developed and described in detail: a delay-line-based phase detector, high-resolution digital frequency synthesizer, and HR-DPWM. To fully exploit the benefits of digital electronics, reduce power consumption, and save area, the digital core of the controller has been designed completely through asynchronous architecture, eliminating the need of high-speed clock and its related hardware. The mixed-signal controller IC has been designed, implemented, and fabricated in 0.18-μm 5-V CMOS process, resulting in effective silicon area of 0.6 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . To demonstrate the mixed-signal controller IC in closed-loop operation of a wireless power system, an experimental 20-W resonant capacitive-based WTP system has been designed and validated. The effectiveness of the controller is well demonstrated and evaluated at the MHz range up to 200 mm misalignment, meeting the strict requirements of resonant-based WPT systems.

Digital Multiphase PWM Integrated Module Generated from a Single Synchronization Source

This article introduces a new architecture for a high-resolution digital pulsewidth modulator (HR-DPWM), which generates multiple output phases, all synchronized and derived out of a single reference source. Constructed through digital standard-cell delay chain and simple combinatorial logic, the module produces PWM signals with configurable on-time, period and time-delay (between phases) with resolution of a single delay element. To minimize the statistical error spread (e.g., jitter error) between phases, a single delay-line is utilized to generate a master time-base while combinatorial logic assigns per-phase independent duty-ratio settings. The resultant module minimizes the time-diversity error between phases, as any uncertainty in the on-time generation is identical between phases. The solution is compact, flexible and scales with the number of phases. Since the entire architecture is realized through standard cells, the solution also scales with fabrication technology and is described by HDL, which translates onto hardware using automated process. The HR-DPWM module has been designed and fabricated on a 0.18 μm 5 V CMOS process, totaling 0.08 mm2 of effective silicon area. Experimental results of a four phase 13-bit HR-DPWM are provided, demonstrating high accuracy and linearity characteristics with time resolution of 200 ps and excellent matching and tracking between all phases.

A High Resolution DPWM Based on Synchronous Phase-Shifted Circuit and Delay Line

In this paper, a hybrid architecture of digital pulse width modulator (DPWM) with high resolution is proposed. Furthermore, to enhance linearity performance, the critical path is optimized by a novel synchronous phase-shifted circuit. A carry chain-based delay line is also utilized to improve time resolution. A 14-bit DPWM with the proposed architecture is implemented and tested by Altera Cyclone IV FPGA. The experiment results show that the DPWM achieves high linearity, where $R^{2}$ maintains over 0.9994. Besides, the output duty cycle covers a wide range from 0.9429% to 99.2% and the time resolution is about 41.3ps.

Design of a DC–DC Converter Customized for Ultra-Low Voltage Operating IoT Platforms

With remarkable advances in IoT, big data, and AI, the fourth industrial revolution is upon us. Low power design methodologies and techniques have been greatly contributing to these advancements by addressing the critical issue of how to increase the device service life under a fixed and limited energy source. In particular, ultra-low power (ULP) technology, which exploits ultra-low voltage (ULV) operating circuit, has recently emerged as a cutting-edge technology for realizing ULP devices. Although a number of studies on ULV circuits have been made so far, and the results have been very successful, research on DC–DC converters optimized for the ULV operation must be carried out in order to use them ultimately in ULP devices. In this paper, a DC–DC converter with low power, small area, and high-resolution digital pulse width modulator (DPWM) for ultra-low voltage (ULV) operating IoT platforms is presented. The proposed DPWM design uses a much smaller number of D flip-flops than conventional ones, achieving significant power saving and area reduction while showing excellent resolution of power conversion. In addition, by utilizing the proposed DPWM, the DC–DC converters can take full advantage of the dynamic switch width modulation technology without overhead, greatly improving the power conversion efficiency under ultra light load conditions. A prototype DC–DC converter with the proposed DPWM is fabricated in Samsung 65nm technology, and the experimental work with this converter and a target ULV operating platform demonstrates that this converter is best suited for the target platform.

A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM

This paper presents a wide-voltage-range, fast-transient all-digital buck converter using a high-resolution digital pulsewidth modulator (DPWM). The converter employs the multithreshold-voltage band-control technique to shorten its transient response. The DPWM uses an all-digital delay-locked loop (ADDLL) to control its cycle. The usage of ADDLL leads to the DPWM possessing a small area while maintaining high cycle resolution. Moreover, the proposed ADDLL-based cycle-controlled DPWM can achieve synchronization between its input and output. This decreases the loop delay of the proposed converter so that the system is easy to be stabilized. The prototype chips of both the ADDLL-based cycle-controlled DPWM and the all-digital buck converter are fabricated in 0.35- $\mu \text{m}$ CMOS process. Measurement results of the cycle-controlled DPWM show that the duty cycle of its output is adjustable from 1% to 99% in a 0.78% increment per step when operating at 1 MHz. The measured transition time of the all-digital buck converter is $ when the load current changes from 50 to 500 mA, and vice versa.

Field‐programmable gate array‐based linear–non‐linear control with high‐resolution digital pulse width modulator and high‐speed embedded analogue‐to‐digital converter for multi‐phase voltage regulator modules

Power converters for applications with high switching frequency and tight output voltage regulation such as voltage regulator modules (VRM) for microprocessors power supplies require fast dynamic response to meet the specifications. An existing control technique known as linear-non-linear (LnL) control strategy allows improving the transient converter response by means of an easy rule for the saturation of the duty cycle. The use of a digital implementation can optimise the transient response of the multi-phase VRM with LnL. However, digital control leads to other problems derived from time discretisation and finite word length effects. The limited resolution and the sampling delay are critical issues for digital control implementation of multi-phase VRM with LnL control. As a result, a high-resolution digital pulse width modulator (DPWM) and high-speed analogue-to-digital (A/D) converter are required to obtain proper performance of the converter. This study is focused on the digital implementation of the well-known LnL control in a multi-phase VRM taking advantage of low-cost field-programmable gate array resources. A detailed description of the digital implementation of the main converter control blocks, which are the A/D converter, the compensator and the DPWM, is provided in the paper.

Monolithic digitally controlled buck converter with TDC-based ADC sharing delay cells with DPWM

Proposed is a monolithic digitally controlled buck converter with a time-to-digital converter based ADC (TDC-based ADC) sharing delay cells with a digital pulse-width modulator (DPWM). The delay cells in the high resolution DPWM are employed as the time reference for the TDC-based ADC, which eliminates the need for an independent delay line. The ADC has a large dynamic range with no penalty of increase of power consumption, which is suitable for sophisticated controls requiring a large ADC dynamic range.

Multimode high-resolution DPWM for RF class-D amplifiers

This paper describes a multimode high-resolution digital pulse width modulator. This modulator, based on a novel hybrid structure, not only has a programmable duty cycle but also realizes phase modulation. A 576 ps pulse resolution is achieved based on a 13.56 MHz switching frequency for near field communication. Fabricated in a SMIC 0.18-μm EEPROM CMOS process, the total area of modulator is only 130 × 180 μm2. Measurement results validate the multi-mode modulation function and high pulse resolution.

High Resolution FPGA DPWM Based on Variable Clock Phase Shifting

This letter proposes a very high resolution digital pulsewidth modulator (DPWM) architecture that takes advantage of a field-programmable gate array (FPGA) advanced clock management capability - the fine phase shifting of the clock. This feature is available in almost every FPGA nowadays, thus allowing very small and programmable delays between the input and output clocks. An original use of this fine phase shifting pushes the limits of DPWM resolution. The experimental results show a time resolution of 19.5 ps in a Virtex-5 FPGA.

Analysis of Process-Dependent Maximal Switching Frequency, Choke Effect, and Its Relaxed Solution in High-Resolution DPWM

This letter uses the fanout-of-4 (FO4) metric to analyze the semiconductor process (SP) dependent maximal switching frequency (MSF) of a digital pulsewidth modulator (DPWM). After discussing the choke effect in a self-oscillating hybrid (SOH) DPWM and its impact on MSF, this letter further shows that separating the voltage-controlled oscillator (VCO) and the delay mux line is an effective way to relax the choke effect so that the MSF in the SOH could be almost doubled, together with 10%-20% power saving. Taking a low-cost AMI06 SP and 9-bit-resolution specification as an example, this letter predicts that 8 MHz switching frequency could be achieved with the proposed SOH. The SOH chip was custom-designed and fabricated in a 0.703 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die via the metal oxide semiconductor implementation service (MOSIS) educational program. The chip test demonstrated that the MSF is 7.4 MHz with 1.07 mA power consumption, and the adjustable switching frequency range is from 1.8 to 7.4 MHz.