High Purity Semi-insulating Substrates Research Articles

Demonstration of SiC n-channel MOSFETs fabricated on a high-purity semi-insulating substrate and investigation of the short-channel effects

N-channel MOSFETs fabricated on a high-purity semi-insulating (HPSI) 4H-SiC substrate were demonstrated. The fabricated MOSFETs exhibited normally-off transistor operation and the peak field effect mobility (μ FE,peak) was 30 cm2 V−1 s−1, which was lower than that of the p−-body MOSFETs (N A = 2 × 1015 cm−3). The critical channel length (L crit) was 1.48 μm for the HPSI MOSFETs, which was shorter than that for the p−-body MOSFETs. In the HPSI MOSFETs, electrons trapped by the compensating defects in the HPSI substrate increase as the Fermi level moves up, which may be the main cause for the resulting low μ FE,peak and short L crit.

Nearly Ideal Breakdown Voltage Observed in Lateral p-i-n Diodes Fabricated on a SiC High-Purity Semi-Insulating Substrate

Lateral p-i-n diodes with small i-region width (less than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5 ~\mu \text{m}$ </tex-math></inline-formula> ) were fabricated by direct ion implantation into a high-purity semi-insulating silicon carbide (SiC) substrate. The breakdown voltage of the diodes increased with increasing the i-region width and a lateral effective breakdown electric field of 1.7–1.9 MV/cm was obtained. The experimental breakdown voltage well agreed with the technology computer-aided design (TCAD) simulation, indicating that deep levels contributing the semi-insulating property do not seriously deteriorate the breakdown voltage in case of the small i-region width.

Carrier Trapping Effects on Forward Characteristics of SiC p-i-n Diodes Fabricated on High-Purity Semi-Insulating Substrates

Carrier trapping effects of high-concentration deep levels in high-purity semi-insulating (HPSI) silicon carbide (SiC) substrates on device characteristics were investigated. Vertical p-i-n diodes were fabricated on HPSI 4H-SiC substrates with ion implantation processes. The fabricated diodes showed good rectification. The experimental forward current&#x2013;voltage (<inline-formula> <tex-math notation="LaTeX">${I}$ </tex-math></inline-formula>&#x2013;<inline-formula> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula>) characteristics were analyzed by using drift-diffusion (DD) simulation that considers deep levels both as recombination centers and carrier traps. The DD simulation revealed that high-concentration carrier traps flatten the potential distribution in the i-type region and, therefore, increase the recombination current and ideality factor in the low-bias region. The simulated <inline-formula> <tex-math notation="LaTeX">${I}$ </tex-math></inline-formula>&#x2013;<inline-formula> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> characteristics assuming a high trap density of <inline-formula> <tex-math notation="LaTeX">$5 \times {10}^{16} \mathrm { \text {cm}^{-{3}}}$ </tex-math></inline-formula> showed good agreement with experimental ones in the temperature range of 295&#x2013;600 K.

(Invited) SiC Lateral Mosfet Implemented on Semi-Insulating Substrate

In most cases, lateral SiC MOSFETs implemented on a SiC epitaxial layer which grown on off-axis conducting substrate. For 4H-SiC, 4º-off toward <11-20> substrate is widely used in order to avoid polytype inclusion. However, step bunching often occurs during the epitaxial growth and high temperature activation process. The step bunching makes surface rough and causes scattering of carriers at the surface. Consequently, the channel mobility of the lateral MOSFET implemented on epitaxial layer grown on off-axis substrate is reduced. Therefore, on-axis substrate has advantages for improving static characteristics compared to the off-axis substrate. However, it is still possible to create polytype inclusion on an on-axis substrate during epitaxial growth, and elimination of epitaxial layer is preferred in many aspects. In this research, 4H-SiC lateral double implanted MOSFET (LDIMOSFET) have been designed and fabricated on an on-axis high purity semi-insulating (HPSI) substrate for the first time. To avoid the step bunching and polytype inclusion problem, we used on-axis SiC substrate without epitaxial layer. Figure 1 shows a cross-sectional view of the LDIMOSFET. As shown in the figure, proposed LDIMOSFET adopted a current path layer (CPL) instead of an epi-layer of the conventional lateral MOSFET. All regions of the LDIMOSFET were formed by ion-implantation. The CPL region plays an important role in obtaining MOSFET characteristics. At a forward bias condition, the CPL serves as a current path of the device, and at reverse bias condition, it serves to support the breakdown voltage. Without CPL region, only the semi-insulating layer exists between the p-base and n+ drain region. In this case, due to a low concentration of the semi-insulating substrate, small value of forward current will flow. Therefore, for obtaining desired forward and reverse characteristics, it is important to optimize the CPL parameters such as doping concentration (NCPL), depth (DCPL), and length (LCPL). To optimize the CPL parameters, device simulations were performed by using device simulator Silvaco-ATLAS. In order to obtain high breakdown voltage and low specific on-resistance, NCPL and DCPL should be within range of 2 × 1016 ≤ NCPL ≤ 4 × 1016/cm3 and 0.2 ≤ DCPL ≤ 0.3 μm, respectively. For device fabrication, considering the simulation results, we used NCPL = 2 × 1016 /cm3, and DCPL = 0.3 μm, respectively. Breakdown voltage and specific on-resistance are also depends on LCPL. Therefore, to find out the effect of LCPL on the breakdown voltage and specific on-resistance, LCPL was varied from 5 to 20 μm. For device fabrication, on-axis HPSI 4H-SiC wafers were used. To find out the effect of CPL region on the device characteristics, LDIMOSFET without CPL is also fabricated. The extracted channel mobility of the LDIMOSFET is 21.7 cm2/V∙s. The reported mobility of the Al-implanted MOSFETs fabricated on the on-axis epitaxial layer is 9 to 19 cm2/V∙s, and they explain that the mobility increase is due to the lower surface roughness. We used on-axis HPSI substrate to avoid the surface roughness scattering caused by the step bunching and we observed mobility comparable to those measured in the device implemented on the epitaxial grown on the on-axis wafer. Figure 2 shows measured IDS – VDS characteristics of the LDIMOSFET when LCPL = 5 μm. As shown in the figure, the highest drain current is 22mA/mm. In contrast, currents in the LDIMOSFET without CPL slightly increase when drain voltage exceeds 10 V. A specific on-resistance of the LDIMOSFET is 17.2 mΩ∙cm2 at VG = 25 V and VD = 1 V. When LCPL was increased from 5 to 20 μm, the specific on-resistance of the device also increased, from 17.2 to 89.8 mΩ∙cm2. The breakdown voltage of LDIMOSFET depends on LCPL, DCPL, and NCPL. Figure 3 shows measured breakdown voltage for different LCPL. As shown in the figure, longer LCPL shows higher breakdown voltage, and the maximum breakdown voltage of 1093 V was observed when LCPL = 20 μm. Maximum breakdown voltage of 1093 V was achieved with low specific on-resistance of 89.8 mΩ∙cm2 at LCPL = 20 μm. The figure of merit (BV2/Ron,sp) of the fabricated LDIMOSFET is 13.3 MW/cm2. The breakdown voltage and specific on-resistance of the device can be improved by adopting field plate and RESURF principle. The effect of the field plate and RESURF principle is under investigation. We will discuss about the detailed effects of the field plate, RESURF principle and device parameters on the static characteristics of the fabricated LDIMOSFET at the manuscript. Figure 1

Electrical properties of n- and p-type 4H-SiC formed by ion implantation into high-purity semi-insulating substrates

Phosphorus or aluminum ions were directly implanted into semi-insulating 4H-SiC substrates with no epitaxial layers to form n- or p-type layers, respectively, with doping densities in the range from 1017 to 1019 cm−3. The electrical properties of these implanted layers annealed at 1650 °C were characterized by Hall effect measurements in the temperature range of 160–900 K. The electrical activation ratios of implanted dopants were 88–98%. The density of compensating defects was higher in Al+-implanted layers than in P+-implanted ones. The mobilities of the implanted layers were mostly comparable to those of epitaxial layers in the doping range investigated.

Thermal Stability of Deep-Level Defects in High-Purity Semi-Insulating 4H-SiC Substrate Studied by Admittance Spectroscopy

Effects of high temperature treatments on the deep-level defects in high-purity semi-insulating substrates are studied by employing electrical and chemical analyses. Thermal admittance spectroscopy reveals the presence of a deep-level defect, labeled XMID, with a state near the middle of the bandgap, playing a decisive role to realize the semi-insulating characteristics. The concentration of the XMID level decreases with increasing treatment temperature from 1400 to 1700 °C, and consequently, the substrate becomes more conductive toward p-type due to residual boron impurities. The identity of XMID is yet to be known but the carbon vacancy is briefly discussed as a possible candidate.

An improved analytical model of 4H-SiC MESFET incorporating bulk and interface trapping effects

An improved analytical model for the current—voltage (I–V) characteristics of the 4H-SiC metal semiconductor field effect transistor (MESFET) on a high purity semi-insulating (HPSI) substrate with trapping and thermal effects is presented. The 4H-SiC MESFET structure includes a stack of HPSI substrates and a uniformly doped channel layer. The trapping effects include both the effect of multiple deep-level traps in the substrate and surface traps between the gate to source/drain. The self-heating effects are also incorporated to obtain the accurate and realistic nature of the analytical model. The importance of the proposed model is emphasised through the inclusion of the recent and exact nature of the traps in the 4H-SiC HPSI substrate responsible for substrate compensation. The analytical model is used to exhibit DC I–V characteristics of the device with and without trapping and thermal effects. From the results, the current degradation is observed due to the surface and substrate trapping effects and the negative conductance introduced by the self-heating effect at a high drain voltage. The calculated results are compared with reported experimental and two-dimensional simulations (Silvaco®-TCAD). The proposed model also illustrates the effectiveness of the gate—source distance scaling effect compared to the gate—drain scaling effect in optimizing 4H-SiC MESFET performance. Results demonstrate that the proposed I–V model of 4H-SiC MESFET is suitable for realizing SiC based monolithic circuits (MMICs) on HPSI substrates.

The Role of Substrate Compensation on DC Characteristics of 4H-SiC MESFET with Buffer Layer: A Combined Two-Dimensional Simulations and Analytical Study

An analytical model of 4H-SiC metal semiconductor field effect transistor (MESFET) is proposed with buffer layer on high purity semi-insulating (HPSI) 4H-SiC substrate compensated by multiple deep level traps. The contribution of deep level traps (DLT) is projected and verified using two-dimensional simulations (Silvaco®). The modeled DC characteristics are compared with two-dimensional simulations performed on the same device as considered in the analytical model.The 4H-SiC MESFET is simulated with and without the effect of buffer layer and the electron concentration profiles in different regions are observed from two-dimensional simulations.The electron concentration profiles obtained at channel-substrate interface clearly shows that when the buffer layer is not present, the channel electrons get trapped by the deep level traps used for substrate compensation. It is also observed that the inclusion of buffer layer minimizes the extent of electron trapping by screening out the active channel from the substrate. However, the trapping phenomena take place in both the cases.We believe that the proposed model of 4H-SiC MESFET which includes the substrate compensation through multiple deep level traps may be useful for realizing SiC based monolithic circuits (MMICs) on HPSI substrates.

Demonstration of 3500-V 4H-SiC Lateral MOSFETs

High-voltage 4H-SiC lateral MOSFETs with different gate layouts, channel lengths, and drift region lengths were fabricated on the (0001) face of a high-purity semi-insulating substrate. A breakdown voltage of 3520 V was achieved on a circular gate device with a channel length of 5 μm and a drift region length of 80 μm. This is, to the best knowledge of the authors, the highest value among 4H-SiC lateral MOSFETs ever reported. The specific on-resistance is 600 mΩ-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , which results in a figure-of-merit (BV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">onsp</sub> ) of 20.6 MW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , which is comparable with other 4H-SiC lateral MOSFETs reported in the literature. It was found that the use of a circular gate layout effectively reduces the reverse leakage current at high voltages.

Preliminary Investigation of Laser Induced Photoconductivity in 4H-SiC PiN Diodes and HPSI Substrate

We present photoconductivity experiments on a 4H-SiC diode and on 4H-SiC high purity semi-insulating (HPSI) substrate. These devices have been tested over a wide optical wavelength range: 355 nm to 820 nm. The penetration depth of optical wavelength has been estimated from spectrophotometer measurements. Photoconductivity regime has been studied at low electrical field for both devices and photoconductivity efficiency has been compared to Si switches.

Microwave power and simulation of S-band SiC MESFETs

In this paper we report our research on DC and S parameter simulations and DC and RF characteristics experimental results of 4H–SiC MESFETs on a high purity semi-insulating substrate. 4H-SiC MESFETs were fabricated using home-grown epi structures. We designed our own devices process to fabricate n-channel 4H–SiC MESFETs with 200μm gate periphery. At a frequency of 2GHz and at 79V drain voltage, the maximum output power density CW is measured to be 7.8W/mm, with a gain of 11.9dB, and power-added efficiency 40%. The cut-off frequency (fT) and the maximum oscillation frequency (fmax) is 8.7GHz and 25.5GHz, respectively. The simulation result of fT and fmax is 11.4GHz and 38.6GHz, respectively.

Physical simulations and experimental results of 4H-SiC MESFETs on high purity semi-insulating substrates

In this paper we report on DC and RF simulations and experimental results of 4H-SiC metal semiconductor field effect transistors (MESFETs) on high purity semi-insulating substrates. DC and small-signal measurements are compared with simulations. We design our device process to fabricate n-channel 4H-SiC MESFETs with 100 μm gate periphery. At 30 V drain voltage, the maximum current density is 440 mA/mm and the maximum transconductance is 33 mS/mm. For the continuous wave (CW) at a frequency of 2 GHz, the maximum output power density is measured to be 6.6 W/mm, with a gain of 12 dB and power-added efficiency of 33.7%. The cut-off frequency (fT) and the maximum frequency (fmax) are 9 GHz and 24.9 GHz respectively. The simulation results of fT and fmax are 11.4 GHz and 38.6 GHz respectively.

4H-SiC Planar MESFETs on High-Purity Semi-Insulating Substrates

Planar MESFETs were fabricated on high-purity semi-insulating (HPSI) 4H-SiC substrates. The saturation drain current of the fabricated MESFETs with a gate length of 0.5 μm and a gate width of 100 μm was 430 mA/mm, and the transconductance was 25 mS/mm. The maximum oscillation frequency and cut-off frequency were 26.4 GHz and 7.2 GHz, respectively. The power gain was 8.4 dB and the maximum output power density was 2.8 W/mm for operation of class A at CW 2 GHz. MESFETs on HPSI substrates showed no current instability and much higher output power density in comparison to MESFETs on vanadium-doped SI substrates.

Electro-thermal simulations of a microwave 4H-SiC MESFET on high purity semi-insulating substrate

DC and small-signal electro-thermal simulations of a 4H-SiC microwave power MESFET on a high purity semi-insulating substrate are compared to measurements. The focus is on the electron transport, substrate traps, and thermal heating. The doping concentrations are described by measured SIMS profiles, and the material parameters are in accordance with published results. Although the simulated MESFET has a p-buffer and a high purity substrate, the simulations show that the density of shallow traps affects the device characteristics. The very good agreement between simulated and measured DC and small-signal characteristics indicates that the models for electron mobility, substrate traps, and heating are the most important to achieve good agreement with measured data.

Fabrication of 4H-SiC Planar MESFETs on High-Purity Semi-Insulating Substrates

4H-SiC planar MESFETs were fabricated using ion-implantation on high-purity semi-insulating substrate, and their DC and RF performances were characterized. A modified RCA method was used to clean the substrate before each procedure. Sacrificial oxide was grown after channel layer etching to eliminate plasma damage to the gate region. A thin, thermal oxide layer was grown to passivate the surface and then a thick field oxide was deposited by CVD. The maximum oscillation frequency of 26.4 GHz and the cut-off frequency of 7.2 GHz were obtained. The power gain was 8.4 dB and the output power was 2.8 W/mm at 2 GHz.

Deep Level Point Defects in Semi-Insulating SiC

The high resistivity of SiC required for many device applications is achieved by compensating residual donors or acceptors with vanadium or intrinsic defects. This work addresses the defect levels of substitutional vanadium and the positively charged carbon vacancy (VC +) in semiinsulating (SI) SiC. After reviewing the earlier studies related to both defects, the paper focuses on temperature-dependent Hall measurements and photo-induced electron paramagnetic resonance (EPR) experiments of 4H and 6H SI SiC. In vanadium-doped samples, a V3+/4+ level near Ec-1.1 eV (4H) and Ec-0.85 eV (6H) is estimated by a comparison of dark EPR spectra and the activation energy determined from the Hall data, assuming that vanadium controls the Fermi level. In high purity semiinsulating substrates, analysis of time-dependent and steady-state photo-EPR data suggests that the plus-to-neutral transition of the carbon vacancy involves a structural relaxation of about 0.6 eV.

Characterization of Semi-insulating SiC

AbstractElectron paramagnetic resonance was used to study defects in high-purity semi-insulating (HPSI) substrates grown by high-temperature chemical vapor deposition and physical vapor transport. Deep level defects associated to different thermal activation energies of the resistivity ranging from ~0.6 eV to ~1.6 eV in HPSI substrates are identified and their roles in carrier compensation processes are discussed. Based on the results obtained in HPSI materials, we discuss the carrier compensation processes in vanadium-doped SI SiC substrates and different activation energies in the material.

High-Purity Versus High-Defect-Density Semiinsulating Substrates for SiC MESFET: Simulation of Device Characteristics

Quantitative assessment of the influence of deep traps in semiinsulating (SI) SiC substrates on transient behavior and substrate leakage current of SiC MESFET is reported. Twodimensional device simulation confirmed that favorable reduction of the current-collapse happens when a fully depleted buffer is used. Simultaneously, the high-purity buffer causes an undesirable increase of the current bypassing the physical channel. A similar and even more pronounced effect is observed when very high purity SI substrates are used. The deep level-induced transient behavior disappears for the concentration of deep acceptor traps below the order of 1x1015 cm-3. However, this low trap concentration results in a virtual inability to pinch-off the channel even at very high gate biases. It has been demonstrated that the electric field preventing electron injection from thechannel into the substrate is very sensitive to the initial charge state of the traps prior to device biasing, which in turn is determined by the energy position of the deep levels in the substrate.

RF Performance and Reliability of SiC MESFETs on High Purity Semi-Insulating Substrates

RF Performance and Reliability of SiC MESFETs on High Purity Semi-Insulating Substrates

High-purity semi-insulating 4H-SiC for microwave device applications

High-purity, semi-insulating (HPSI) 4H-SiC crystals with diameters up to 75 mm have been grown by the seeded sublimation technique without the intentional introduction of elemental deep-level dopants, such as vanadium. Wafers cut from these crystals exhibit homogeneous activation energies near mid gap and thermally stable semi-insulating (SI) behavior (>109 ohm-cm) throughout device processing. Secondary ion mass spectroscopy, deep-level transient spectroscopy, optical admittance spectroscopy, and electron paramagnetic resonance data suggest that the SI behavior originates from several deep levels associated with intrinsic point defects. Micropipe densities in HPSI substrates have been demonstrated to be as low as 10 cm−2 in 2-in. substrates, and the room-temperature thermal conductivity of this material is near the theoretical maximum of 5 W/cm·K for 4H-SiC. Devices fabricated on these HPSI wafers do not exhibit any substrate related back-gating effects and have power densities as high as 5.2 W/mm with 63% power added efficiency.