High-power Power Amplifier Research Articles

A 124-to-152-GHz Power Amplifier Exploiting Chebyshev-Type Two-Section Wideband and Low-Loss Power-Combining Technique in 28-nm CMOS

This article presents a high-power wideband power amplifier (PA) with a four-way power-combining technique for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$D$</tex-math> </inline-formula> -band high-resolution radar. The power combiner is based on a two-section Chebyshev impedance converter to achieve a large bandwidth (BW) and is realized with slow wave coplanar waveguides (S-CPWs) to reduce the insertion loss and chip area. Therefore, our developed technique can provide broadband and low-loss power-combining scheme in a very compact size. A high-power PA with four-way combining has been fabricated in a 28-nm CMOS bulk technology. The unit PA uses low- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$k$</tex-math> </inline-formula> transformer-based coupled-resonator networks to realize wideband matching. The measured results of the PA prototype demonstrate the peak gain of 22.6 dB, the saturated output power of 16.2 dBm, and the peak power added efficiency of 8.6% at 135 GHz with a 3-dB BW of 28 GHz from 124 to 152 GHz. Meanwhile, the total area of this PA die is merely 0.66 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 0.73 mm.

A 60-GHz 32-Way Hybrid Power Combination Power Amplifier in 55-nm Bulk CMOS

This article presents a high output power <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V$ </tex-math></inline-formula> -band power amplifier (PA) with 32-way power combining in 55-nm bulk CMOS. A new hybrid power combiner (HPC) is proposed and utilized to output combination network of PA. Incorporating the impedance matching requirements, a general model and analysis equations are given, from which it can be seen that HPC increases the design flexibility and reduces the difficulty of multiway power combiner using a single approach, while simultaneously considering asymmetry caused by parasitic capacitance and chip layout distribution. The adoption of HPC also takes into account the inconsistencies between the internal and external channels of the chip due to thermal distribution, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$R$ </tex-math></inline-formula> drop, and so on. To the best of our knowledge, this is the first time that the challenges and considerations of high-power PA design in silicon-based process are comprehensively presented, and two test printed circuit boards (PCBs) are used to compare and improve the thermal problem of high-power PAs during testing. The PA achieves a small-signal gain of 21.9 dB at 60 GHz and a saturated output power of 24.42–25.06 dBm at 57–62 GHz with a maximum output 1-dB compression point of 21.87 dBm and a peak power-added efficiency (PAE) of 11%. The core area is 1.77 mm2.

220-240-GHz High-Gain Phase Shifter Chain and Power Amplifier for Scalable Large Phased-Arrays

This paper focuses on the design aspects of the key components for a scalable phased-array system over the 200 GHz frequency range. A high-gain phase shifter chain for 220 to 240 GHz frequency range and a high-gain power amplifier (PA) with a high output power are designed in a 0.13-μm SiGe BiCMOS technology. The phase shifter chain includes a low-noise amplifier (LNA), a vector modulator phase shifter (PS), and a gain-enhancing amplifier. The LNA is a five-stage cascode design. The vector modulator core is realized by two variable gain amplifiers based on the Gilbert cell architecture. A four-stage cascode design is used for the gain-enhancing amplifier. The phase shifter chain shows a measured gain of 18 dB at 230 GHz with a 360° phase tuning range and more than 10 dB of gain control. The chip achieves a minimum measured noise figure of 11.5 dB at 230 GHz and shows a wideband noise characteristic. The complete phase shifter chain chip consumes a dc power of 153 mW and occupies a 1.41 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area. A high-power PA that is critical for a large phased-array system is designed. This paper presents a unique 4-way power combining technique utilizing a differential quadrature coupler. The realized balanced PA occupies an area of 0.67 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and shows a measured peak gain of 21 dB at 244 GHz. The PA consumes 819 mW of dc power and delivers a maximum saturated output power ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P_sat</i> ) of 7.1 dBm at 244 GHz and more than 4.3 dBm of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P_sat</i> from 230 to 255 GHz.

High-Efficiency E-Band Power Amplifiers and Transmitter Using Gate Capacitance Linearization in a 65-nm CMOS Process

This brief presents a new design technique for high-efficiency CMOS millimeter-wave power amplifiers (PAs) and the implementations of a two-stage moderate-power PA, a three-stage high-power PA, and a transmitter all working over 68–78 GHz. The proposed PAs adopt nMOS capacitors connected at the gates of the transistors of the last one or two amplifying stages to compensate for the gate capacitance variation over a large signal swing, thus improving the linearity and the power efficiency. Implemented in a 65-nm CMOS process, the two-stage PA achieves a peak power-added efficiency (PAE) of 24.2%, a maximum gain of 17 dB, and a 3-dB bandwidth from 68 to 78 GHz. The three-stage PA achieves a saturated power (Psat) of 17.3 dBm, a peak PAE of 18.9%, and a maximum gain of 21.4 dB. The transmitter consisting of the three-stage PA and a passive double-balanced mixer with local oscillator shaping technique achieves a Psat of 14.6 dBm, a peak efficiency of 13.9%, and a conversion gain of 15.6 dB.

Behavioral modeling of nonlinear RF power amplifiers using ensemble SDBCC network

A new behavioral model of nonlinear RF power amplifiers (PA) is presented to treat memory effects. The key issue here is considering the phenomenon that uplink quadrature modulation signals are influenced not only by the current uplink signals, but also by previous terms. The variation of AM/AM and AM/PM, and the asymmetries in lower and upper intermodulation terms are frequently observed in high-power PAs. To treat these phenomena, this paper proposes a model based on artificial neural network. The contribution made of this model is to solve the order determination issue (determining the order of the previous output and input signals that have influence on the current output signal). In addition, the recognized difficulty of long training process is overcome by using SDBCC algorithm, a novel neural network design method combining structure decomposition and the Cascade-Correlation neural network algorithm. The required maximum delay is established by examining the autocorrelation coefficient of the residual error. Ensemble system is finally used to improve the performance further. This proposed method is successfully validated in nonlinear modeling of the RF PAs from HuaWei Company, including 8000 samples.

Design and implement of transceiver system for hybrid rocket with coplanar wraparound antenna at 433 MHz

This study aims to implement the telematics between hybrid rockets and the ground receiving station. In order to significantly reduce the rocket weight, fibre-reinforced plastic is used for the hybrid rocket casing, on which coplanar wraparound antennas with an operating frequency of 433 MHz are designed. The antenna structure contains three coplanar printed patches, among which the middle printed patch is the primary radiator and the resonant length appears a wavelength for the metallic surface case. An RF module with high receiver sensitivity and a high-power power amplifier are included to enhance the communication coverage of hybrid rockets and the ground receiving station so that the station can effectively track the hybrid rocket. Finally, the radio wave propagation model is used for calculating the link budget such that the communication coverage between rocket transmitters and the ground receiving station can be estimated, and on-site measurement and verification are preceded.

Spectral Efficiency and Energy Efficiency of OFDM Systems: Impact of Power Amplifiers and Countermeasures

In wireless communication systems, the nonlinear effect and inefficiency of power amplifier (PA) have posed practical challenges for system designs to achieve high spectral efficiency (SE) and energy efficiency (EE). In this paper, we analyze the impact of PA on the SE-EE tradeoff of orthogonal frequency division multiplex (OFDM) systems. An ideal PA that is always linear and incurs no additional power consumption can be shown to yield a decreasing convex function in the SE-EE tradeoff. In contrast, we show that a practical PA has an SE-EE tradeoff that has a turning point and decreases sharply after its maximum EE point. In other words, the Pareto-optimal tradeoff boundary of the SE-EE curve is very narrow. A wide range of SE-EE tradeoff, however, is desired for future wireless communications that have dynamic demand depending on the traffic loads, channel conditions, and system applications, e.g., high-SE-with-low-EE for rate-limited systems and high-EE-with-low-SE for energy-limited systems. For the SE-EE tradeoff improvement, we propose a PA switching (PAS) technique. In a PAS transmitter, one or more PAs are switched on intermittently to maximize the EE and deliver an overall required SE. As a consequence, a high EE over a wide range SE can be achieved, which is verified by numerical evaluations: with 15% SE reduction for low SE demand, the PAS between a low power PA and a high power PA can improve EE by 323%, while a single high power PA transmitter improves EE by only 68%.

Implementation of a fully integrated 30-dBm RF CMOS linear power amplifier with power combiner

In this paper, a fully integrated 30-dBm UHF band differential power amplifier (PA) with transformer-type combiner is designed and fabricated in a 0.18-μm CMOS technology. For the high power PA design, proposed transformer network and the number of power cells is fully analyzed and optimized to find inductors dimensions. In order to improve both the linear operating range and the power efficiency simultaneously, a parallel combination of the class AB and the class C amplifier in power cells was employed. The PA delivers an output power of 29dBm and a power-added efficiency of 24% with a power gain of 20dB, including the losses of the bond-wires.

“RF-SoC”: Integration Trends of On-Chip CMOS Power Amplifier: Benefits of External PA versus Integrated PA for Portable Wireless Communications

RFIC integration has seen dramatic progress since the early 1990s. For example, Si-based single-chip products for GSM, WLAN, Bluetooth, and DECT applications have become commercially available. However, RF power amplifiers (PAs) and switches tend to remain off-chip in the context of single-chip CMOS/BiCMOS transceiver ICs for handset applications. More recently, several WLAN/Bluetooth vendors have successfully integrated less demanding PAs onto the transceivers. This paper will focus on single-chip RF-system-on-a-chip (i.e., “RF-SoC”) implementations that include a high-power PA. An analysis of all tradeoffs inherent to integrating higher power PAs is provided. The analysis includes the development cost, time-to-market, power efficiency, yield, reliability, and performance issues. Recent design trends on highly integrated CMOS WiFi transceivers in the literature will be briefly reviewed with emphasis on the RF-SoC product design tradeoffs impacted by the choice between integrated versus external PAs.

Behavioral modeling of nonlinear RF power amplifiers considering memory effects

This paper proposes a new behavioral model to treat memory effects in nonlinear power amplifiers (PAs). Phenomena such as asymmetries in lower and upper intermodulation terms, and variation of AM/AM and AM/PM, depending on signal history, are often observed in high-power PAs. To treat these phenomena, this paper presents a model based on the previously developed memory polynomial model. The contribution made in this paper is to augment the memory polynomial model to include a sparse delay tap structure that reduces the parameter space required for accurate model identification. A figure-of-merit, called the memory effect ratio, is defined to quantify the relative level of distortion due to memory effects, as compared to the memoryless portion. Another figure-of-merit is defined as the memory effect modeling ratio, which quantifies the degree to which the PA memory effects have been accounted for in the model. This new technique is validated using a variety of RF PAs, including an 880-MHz and a 2.1-GHz high-power laterally diffused metal-oxide semiconductor PA and various signals such as two-tone, eight-tone, and IS-95B signals.